Wide range 8ps incremental resolution time interval generator based on FPGA technology

Accurate generation of picosecond-resolution wide-range time intervals has become a necessity for the characterization of time-to-digital converters involved in time resolved imaging. This paper presents the design and measurement of a time interval generator based on FPGA technology. Although it can be employed in different automatic test setups, it has been designed to characterize an array of time-to-digital converters. It can work as periodic pulse/ frequency generator but also as a digital-to-time converter. The accuracy of periodic pulse generator is around 20ps RMS jitter over a time range of 600ps to 33ns. The incremental time resolution is 8ps and the repetition rate is up to 2MHz. The accuracy of the digital-to-time converter is less than 0.8LSB DNL and 2LSB INL, whilst the time resolution is 27ps. Full characterization of the module is reported including a comparison with state-of-the-art instruments in this field.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2012-38921- C02, IPT −2011-1625-430000, IPC- 20111009 CDTIJunta de Andalucía TIC 2012–233

On the calibration of a SPAD-based 3D imager with in-pixel TDC using a time-gated technique

The optical characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. The overall full-width half-maximum (FWHM) of the detector ensemble SPAD plus TDC is 690ps. The sensor has been fabricated in a 0.18μm standard CMOS technology which features an average dark-count rate (DCR) of 42kHz at 1V excess voltage (V e ) and room temperature. The detector successfully uses its time-gating capability to mitigate this large amount of noise enabling the sensor for accurate time-of-flight (ToF) measurements. The effectiveness of the time-gating technique is experimentally demonstrated. According to measurements, a time window of 400ns is enough to ensure that the TDC is triggered by light rather than by spurious events.Office of Naval Research (USA) N000141410355Ministerio de Economía y Competitividad TEC2012-38921- C02, IPT- 2011-1625-430000, IPC- 20111009Junta de Andalucía TIC 2012- 233

Accelerating software radio astronomy FX correlation with GPU and FPGA co-processors

Includes abstract.Includes bibliographical references (leaves [117]-121).This thesis attempts to accelerate compute intensive sections of a frequency domain radio astronomy correlator using dedicated co-processors. Two co-processor implementations were made independently with one using reconfigurable hardware (Xilinx Virtex 4LXlOO) and the other uses a graphics processor (Nvidia 9800GT). The objective of a radio astronomy correlator is to compute the complex valued correlation products for each baseline which can be used to reconstruct the sky's radio brightness distribution. Radio astronomy correlators have huge computation demands and this dissertation focuses on the computational aspects of correlation, concentrating on the X-engine stage of the correlator

Sensorless control of surface mounted permanent magnet machine using fundamental PWM excitation

This thesis describes the development of a sensorless control method for a surface mounted permanent magnet synchronous machine drive system. The saturation saliency in the machine is tracked from the stator current transient response to the fundamental space vector PWM (pulse width modulation) excitation. The rotor position and speed signals are obtained from measurements of the stator current derivative during the voltage vectors contained in the normal fundamental PWM sequence. In principle, this scheme can work over a wide speed range. However, the accuracy of the current derivative-measurements made during narrow voltage vectors reduces. This is because high frequency current oscillations exist after each vector switching instant, and these take a finite time to die down. Therefore, in this thesis, vector extension and compensation schemes are proposed which ensure correct current derivative measurements are made, even during narrow voltage vectors, so that any induced additional current distortion is kept to a minimum. The causes of the high frequency switching oscillations in the AC drive system are investigated and several approaches are developed to reduce the impact of these oscillations. These include the development of a novel modification to the IGBT gate drive circuit to reduce the requirement for PWM vector extension. Further improvements are made by modifications to the current derivative sensor design together with their associated signal processing circuits. In order to eliminate other harmonic disturbances and the high frequency noise appearing in the estimated position signals, an adaptive disturbance identifier and a tracking observer are incorporated to improve the position and speed signals. Experimental results show that the final sensorless control system can achieve excellent speed and position control performance

SPATIAL TRANSFORMATION PATTERN DUE TO COMMERCIAL ACTIVITY IN KAMPONG HOUSE

ABSTRACT Kampung houses are houses in kampung area of the city. Kampung House oftenly transformed into others use as urban dynamics. One of the transfomation is related to the commercial activities addition by the house owner. It make house with full private space become into mixused house with more public spaces or completely changed into full public commercial building. This study investigate the spatial transformation pattern of the kampung houses due to their commercial activities addition. Site observations, interviews and questionnaires were performed to study the spatial transformation. This study found that in kampung houses, the spatial transformation pattern was depend on type of commercial activities and owner perceptions, and there are several steps of the spatial transformation related the commercial activity addition. Keywords: spatial transformation pattern; commercial activity; owner perception, kampung house; adaptabilit

Multipass communication systems for tiled processor architectures

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 191-202).Multipass communication systems utilize multiple sets of parallel baseband receiver functions to balance communication data rates and available computation capabilities. This is achieved by spatially pipelining baseband functions across parallel resources to perform multiple processing passes on the same set of received values, thus allowing the system to simultaneously convey multiple sequences of data using a single wireless link. The use of multiple passes mitigates the effects of data rate on receiver processing bottlenecks, making the use of general-purpose processing elements for high data rate communication functions viable. The flexibility of general-purpose processing, in turn, allows the receiver composition to trade-off resource usage and required processing rate. For instance, a communication system could be distributed across 2 passes using 2x the overall area, but reducing the data rate for each pass and the resultant overall required processing rate, and hence clock speed, by 1/2. Lowering the clock speed can also be leveraged to reduce power through voltage scaling and/or the use of higher Vt devices. The characteristics of general-purpose parallel processors for communications processing are explored, as well as the applicability of specific parallel designs to communications processing.(Cont.) In particular, an in depth look is taken of the Raw processor's tiled architecture as a general-purpose parallel processor particularly well suited to portable communications processing. An example of a multipass system, based on the 802.11a baseband, implemented on the Raw processor along with the accompanying hardware implementation is presented as both a proof-of-concept, as well as a means to explore some of the advantages and trade-offs of such a system. A bit-error rate study is presented which shows this multipass system to be within a small fraction of dB of the performance of an equivalent data rate single pass system, thus demonstrating the viability of the multipass algorithm. In addition, the capability of tiled processors to maximize processing capabilities at the system block level, as well as the system architectural level, is shown. Parallel implementations of two processing intensive functions: the FFT and the Viterbi decoder are shown. A parallelized assembly language FFT utilizing 16 tiles is shown to have a 1,000x improvement , and a parallelized 48-tile assembly language Viterbi decoder is shown to have a 10, 000x improvement over corresponding serial C implementations.by Nathan Robert Shnidman.Ph.D

The Italian VLBI Network: First Results and Future Perspectives

A first 24-hour Italian VLBI geodetic experiment, involving the Medicina, Noto, and Matera antennas, shaped as an IVS standard EUROPE, was successfully performed. In 2014, starting from the correlator output, a geodetic database was created and a typical solution of a small network was achieved, here presented. From this promising result we have planned new observations in 2016, involving the three Italian geodetic antennas. This could be the beginning of a possible routine activity, creating a data set that can be combined with GNSS observations to contribute to the National Geodetic Reference Datum. Particular care should be taken in the scheduling of the new experiments in order to optimize the number of usable observations. These observations can be used to study and plan future experiments in which the time and frequency standards can be given by an optical fiber link, thus having a common clock at different VLBI stations