Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design

This paper presents a model for analyzing the reliability of a clockless wave pipeline as an intellectual property (IP) core for embedded design. This design requires different clocking requirements by each embedded IP core during integration. Therefore, either partial or global lack of synchronization of the embedded clocking is considered for the data flow. The clockless wave pipeline represents an alternative to a traditional pipeline scheme; it requires an innovative computing model that is readily suitable for high-throughput computing by heterogeneous IP logic cores embedded in system-on-chip (SoC). A clockless wave pipeline technique relies on local asynchronous operation for seamless integration of a combinational core into an SoC. The basic computational components of a clockless wave pipeline are the datawaves, together with the request signals and switches. The coordination of the processing of the datawaves throughout the pipeline by the request signals is accomplished with no intermediate access in the clock control. Furthermore, the reliability of clockless-wave-pipeline-based cores is of importance when designing a reliable SOC. In this paper, the reliability in the clockless operations of the wave pipeline is analyzed by considering the datawaves and the request signals. The effect of the so-called out-of-orchestration between the datawaves and the request signals (which is referred to as a datawave fault) is proposed in the reliability analysis. A clockless-induced datawave fault model is proposed for clockless fault-tolerant design

Study on the maximum speed and reliability assurance in wave pipeline-based combinational circuits

Scope and Method of Study: Wave pipeline is one of the revolutionary technologies beyond conventional pipeline in the microprocessor architecture research area. Clockless wave pipeline is the cutting-edge and innovative pipeline without relying on clock signal. Due to the stringent requirement for high density and performance of current VLSI technology, reliability is being considered as one of the most crucial issues. Reliability modeling and optimization techniques have been applied extensively. Clock frequency is one of the keys to achieve the fast circuit speed. A clock cycle time optimization and analysis method is proposed in order to achieve a ultra high clock frequency in the context of the proposed new wave pipeline.Findings and Conclusions: The reliability-driven design and optimization techniques for the clockless wave pipeline are proposed. It is mainly focused on the two parts, i.e., request signal and datawave. A more aggressive technology beyond wave pipeline with ultra-high throughput and speed towards maximum circuit frequency is mainly proposed, analyzed, simulated, and verified

Comparision of Different Logic style for High Performance Wave Pipeline Circuit

High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications .Existing logic families cannot provide both of them simultaneously. We propose Double Pass Transistor Logic (DPL) which can be used as a universal logic to provide finest grain pipelining without affecting overall latency or increasing the area. It  does not require  any special process steps and hence, can be  realized  in  a  normal process  technology  as  against  the CPL proposed  by  Yano et  al  [2] which uses  threshold  voltage  adjustment  of  selected  devices.  The design procedure is described for (a) low latency, (b) high throughput and (c) low area requirements. In  addition to the various  advantages,  it  is envisioned  that DPL  designs  can also be used to build ultra-high speed  pipelined system without pipelining latches, viz., wave pipelined  digital systems,  where the throughput achievable  is beyond  that permitted  by  the delay  of  a pipeline stage

A Practical Application of Wave-Pipelining Theory on a Adaptive Differential Pulse Code Modulation Coder-Decoder Design

Pipeline architectures are often considered in VLSI designs that require high throughput. The draw-backs for traditional pipelined architectures are the increased area, power, and latency required for implementation. However, with increased design effort, wave-pipelining can be applied as an alternative to a pipelined circuit to reduce the pipeline area, power, and latency while maintaining the original functionality and timing of the overall circuit. The objective of this paper is the successful application of the theories of wave-pipelining in a practical digital system. To accomplish this, the pipelined portion of an Multi-Channel Adaptive Differential Pulse Code Modulation (ADPCM) Coder-Decoder (CODEC) is replaced with a wave pipeline design

Meshfree Model for Wave-Seabed Interactions Around Offshore Pipelines

The evaluation of the wave-induced seabed instability around a submarine pipeline is particularly important for coastal engineers involved in the design of pipelines protection. Unlike previous studies, a meshfree model is developed to investigate the wave-induced soil response in the vicinity of a submarine pipeline. In the present model, Reynolds-Averaged Navier-Stokes (RANS) equations are employed to simulate the wave loading, while Biot&rsquo s consolidation equations are adopted to investigate the wave-induced soil response. Momentary liquefaction around an offshore pipeline in a trench is examined. Validation of the present seabed model was conducted by comparing with the analytical solution, experimental data, and numerical models available in the literature, which demonstrates the capacity of the present model. Based on the newly proposed model, a parametric study is carried out to investigate the influence of soil properties and wave characteristics for the soil response around the pipeline. The numerical results conclude that the liquefaction depth at the bottom of the pipeline increases with increasing water period (T) and wave height (H), but decreases as backfilled depth ( H b ), degree of saturation ( S r ) and soil permeability (K) increase. Document type: Articl

Floatation of Buried Submarine Pipeline under Cyclic Loading of Water Pressure -Numerical and Experimental Studies-

A dynamic response of a submarine pipeline buried in sandy seabed sediments to water loading generated by harmonically oscillating water-table vertical movements is examined in the present report experimentally and numerically. The aim of small-scale laboratory experiments was: (1) to record time-histories of pipeline vertical displacements, and (2) to observe a shape of slip surface of an overburden sand body involved in breakout together with the pipeline. A parametric study was carried out in order to investigate the influence of two meaningful factors, that is the depth of burial and the specific gravity of pipeline, on a gradual upward displacement of the pipeline. Based on a numerical finite-element 2D-analysis of the hydrodynamic pore pressure and effective stresses oscillations in the pipeline vicinity, an analysis of the pipeline stability potential is presented, in which all the experimental cases tested are verified. All important component forces (e.g., hydrodynamic uplift force) associated with floatation phenomenon of the buried submarine pipeline are considered and quantified