Fault-tolerant sub-lithographic design with rollback recovery

Shrinking feature sizes and energy levels coupled with high clock rates and decreasing node capacitance lead us into a regime where transient errors in logic cannot be ignored. Consequently, several recent studies have focused on feed-forward spatial redundancy techniques to combat these high transient fault rates. To complement these studies, we analyze fine-grained rollback techniques and show that they can offer lower spatial redundancy factors with no significant impact on system performance for fault rates up to one fault per device per ten million cycles of operation (Pf = 10^-7) in systems with 10^12 susceptible devices. Further, we concretely demonstrate these claims on nanowire-based programmable logic arrays. Despite expensive rollback buffers and general-purpose, conservative analysis, we show the area overhead factor of our technique is roughly an order of magnitude lower than a gate level feed-forward redundancy scheme

Superlattice Nanowire Pattern Transfer (SNAP)

During the past 15 years or so, nanowires (NWs) have emerged as a new and distinct class of materials. Their novel structural and physical properties separate them from wires that can be prepared using the standard methods for manufacturing electronics. NW-based applications that range from traditional electronic devices (logic and memory) to novel biomolecular and chemical sensors, thermoelectric materials, and optoelectronic devices, all have appeared during the past few years. From a fundamental perspective, NWs provide a route toward the investigation of new physics in confined dimensions. Perhaps the most familiar fabrication method is the vapor−liquid−solid (VLS) growth technique, which produces semiconductor nanowires as bulk materials. However, other fabrication methods exist and have their own advantages. In this Account, I review a particular class of NWs produced by an alternative method called superlattice nanowire pattern transfer (SNAP). The SNAP method is distinct from other nanowire preparation methods in several ways. It can produce large NW arrays from virtually any thin-film material, including metals, insulators, and semiconductors. The dimensions of the NWs can be controlled with near-atomic precision, and NW widths and spacings can be as small as a few nanometers. In addition, SNAP is almost fully compatible with more traditional methods for manufacturing electronics. The motivation behind the development of SNAP was to have a general nanofabrication method for preparing electronics-grade circuitry, but one that would operate at macromolecular dimensions and with access to a broad materials set. Thus, electronics applications, including novel demultiplexing architectures; large-scale, ultrahigh-density memory circuits; and complementary symmetry nanowire logic circuits, have served as drivers for developing various aspects of the SNAP method. Some of that work is reviewed here. As the SNAP method has evolved into a robust nanofabrication method, it has become an enabling tool for the investigation of new physics. In particular, the application of SNAP toward understanding heat transport in low-dimensional systems is discussed. This work has led to the surprising discovery that Si NWs can serve as highly efficient thermoelectric materials. Finally, we turn toward the application of SNAP to the investigation of quasi-one-dimensional (quasi-1D) superconducting physics in extremely high aspect ratio Nb NWs

A low-power reconfigurable logic array based on double-gate transistors

A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI DG-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly

Nonphotolithographic nanoscale memory density prospects

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations

Fin-array tunneling trigger with tunable hysteresis on (001) silicon substrate

We report the fabrication and characterization of a GaAs fin-array tunneling trigger monolithically integrated on an exact (001) silicon substrate. A Schmitt-trigger-like behavior was observed under double sweep condition by connecting the tunnel diode with an on-chip load resistor. The tunneling trigger circuit was studied using load line analysis. Critical parameters of the circuit were extracted. We found that the circuit hysteresis can be tuned by tailoring of the diode dimensions and load resistor value

Array-based architecture for FET-based, nanoscale electronics

Advances in our basic scientific understanding at the molecular and atomic level place us on the verge of engineering designer structures with key features at the single nanometer scale. This offers us the opportunity to design computing systems at what may be the ultimate limits on device size. At this scale, we are faced with new challenges and a new cost structure which motivates different computing architectures than we found efficient and appropriate in conventional very large scale integration (VLSI). We sketch a basic architecture for nanoscale electronics based on carbon nanotubes, silicon nanowires, and nano-scale FETs. This architecture can provide universal logic functionality with all logic and signal restoration operating at the nanoscale. The key properties of this architecture are its minimalism, defect tolerance, and compatibility with emerging bottom-up nanoscale fabrication techniques. The architecture further supports micro-to-nanoscale interfacing for communication with conventional integrated circuits and bootstrap loading

Wave-guided optical waveguides

This work primarily aims to fabricate and use two photon polymerization (2PP) microstructures capable of being optically manipulated into any arbitrary orientation. We have integrated optical waveguides into the structures and therefore have freestanding waveguides, which can be positioned anywhere in the sample at any orientation using optical traps. One of the key aspects to the work is the change in direction of the incident plane wave, and the marked increase in the numerical aperture demonstrated. Hence, the optically steered waveguide can tap from a relatively broader beam and then generate a more tightly confined light at its tip. The paper contains both simulation, related to the propagation of light through the waveguide, and experimental demonstrations using our BioPhotonics Workstation. In a broader context, this work shows that optically trapped microfabricated structures can potentially help bridge the diffraction barrier. This structure-mediated paradigm may be carried forward to open new possibilities for exploiting beams from far-field optics down to the subwavelength domain. (C)2012 Optical Society of Americ

FPGA dynamic and partial reconfiguration : a survey of architectures, methods, and applications

Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption

High-precision, large-domain three-dimensional manipulation of nano-materials for fabrication nanodevices

Nanoscaled materials are attractive building blocks for hierarchical assembly of functional nanodevices, which exhibit diverse performances and simultaneous functions. We innovatively fabricated semiconductor nano-probes of tapered ZnS nanowires through melting and solidifying by electro-thermal process; and then, as-prepared nano-probes can manipulate nanomaterials including semiconductor/metal nanowires and nanoparticles through sufficiently electrostatic force to the desired location without structurally and functionally damage. With some advantages of high precision and large domain, we can move and position and interconnect individual nanowires for contracting nanodevices. Interestingly, by the manipulating technique, the nanodevice made of three vertically interconnecting nanowires, i.e., diode, was realized and showed an excellent electrical property. This technique may be useful to fabricate electronic devices based on the nanowires' moving, positioning, and interconnecting and may overcome fundamental limitations of conventional mechanical fabrication