Vernier Ring Based Pre-bond Through Silicon Vias Test in 3D ICs

Defects in TSV will lead to variations in the propagation delay of the net connected to the faulty TSV. A non-invasive Vernier Ring based method for TSV pre-bond testing is proposed to detect resistive open and leakage faults. TSVs are used as capacitive loads of their driving gates, then time interval compared with the fault-free TSVs will be detected. The time interval can be detected with picosecond level resolution, and digitized into a digital code to compare with an expected value of fault-free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of time interval 10 ps, resistive open defects 0.2 kΩ above and equivalent leakage resistance less than 18 MΩ. Compared with existing methods, detection precision, area overhead, and test time are effectively improved, furthermore, the fault degree can be digitalized into digital code

A DLL Based Test Solution for 3D ICs

Integrated circuits (ICs) are rapidly changing and vertical integration and packaging strategies have already become an important research topic. 2.5D and 3D IC integrations have obvious advantages over the conventional two dimensional IC implementations in performance, capacity, and power consumption. A passive Si interposer utilizing Through-Silicon via (TSV) technology is used for 2.5D IC integration. TSV is also the enabling technology for 3D IC integration. TSV manufacturing defects can affect the performance of stacked devices and reduce the yield. Manufacturing test methodologies for TSVs have to be developed to ensure fault-free devices. This thesis presents two test methods for TSVs in 2.5D and 3D ICs utilizing Delay-Locked Loop (DLL) modules. In the test method developed for TSVs in 2.5D ICs, a DLL is used to determine the propagation delay for fault detection. TSV faults in 3D ICs are detected through observation of the control voltage of a DLL. The proposed test methods present a robust performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLLs. 3D full-wave simulations are performed to extract circuit level models for TSVs and fragments of an interposer wires using HFSS simulation tools. The extracted TSV models are then used to perform circuit level simulations using ADS tools from Agilent. Simulation results indicate that the proposed test solution for TSVs can detect manufacturing defects affecting the TSV propagation delay

An On-chip PVT Resilient Short Time Measurement Technique

As the CMOS technology nodes continue to shrink, the challenges of developing manufacturing tests for integrated circuits become more difficult to address. To detect parametric faults of new generation of integrated circuits such as 3D ICs, on-chip short-time intervals have to be accurately measured. The accuracy of an on-chip time measurement module is heavily affected by Process, supply Voltage, and Temperature (PVT) variations. This work presents a new on-chip time measurement scheme where the undesired effects of PVT variations are attenuated significantly. To overcome the effects of PVT variations on short-time measurement, phase locking methodology is utilized to implement a robust Vernier delay line. A prototype Time-to-Digital Converter (TDC) has been fabricated using TSMC 0.180 µm CMOS technology and experimental measurements have been carried out to verify the performance parameters of the TDC. The measurement results indicate that the proposed solution reduces the effects of PVT variations by more than tenfold compared to a conventional on-chip TDC. A coarse-fine time interval measurement scheme which is resilient to the PVT variations is also proposed. In this approach, two Delay Locked Loops (DLLs) are utilized to minimize the effects of PVT on the measured time intervals. The proposed scheme has been implemented using CMOS 65nm technology. Simulation results using Advanced Design System (ADS) indicate that the measurement resolution varies by less than 0.1ps with ±15% variations of the supply voltage. The proposed method also presents a robust performance against process and temperature variations. The measurement accuracy changes by a maximum of 0.05ps from slow to fast corners. The implemented TDC presents a robust performance against temperature variations too and its measurement accuracy varies a few femto-seconds from -40 ºC to +100 ºC. The principle of robust short-time measurement was used in practice to design and implement a state-of-the-art Coordinate Measuring Machine (CMM) for an industry partner to measure geometrical features of transmission parts with micrometer resolution. The solution developed for the industry partner has resulted in a patent and a product in the market. The on-chip short-time measurement technology has also been utilized to develop a solution to detect Hardware Trojans

Production and Characterisation of SLID Interconnected n-in-p Pixel Modules with 75 Micrometer Thin Silicon Sensors

The performance of pixel modules built from 75 micrometer thin silicon sensors and ATLAS read-out chips employing the Solid Liquid InterDiffusion (SLID) interconnection technology is presented. This technology, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It allows for stacking of different interconnected chip and sensor layers without destroying the already formed bonds. In combination with Inter-Chip-Vias (ICVs) this paves the way for vertical integration. Both technologies are combined in a pixel module concept which is the basis for the modules discussed in this paper. Mechanical and electrical parameters of pixel modules employing both SLID interconnections and sensors of 75 micrometer thickness are covered. The mechanical features discussed include the interconnection efficiency, alignment precision and mechanical strength. The electrical properties comprise the leakage currents, tuning characteristics, charge collection, cluster sizes and hit efficiencies. Targeting at a usage at the high luminosity upgrade of the LHC accelerator called HL-LHC, the results were obtained before and after irradiation up to fluences of $10^{16}$ $\mathrm{n}_{\mathrm{eq}}/\mathrm{cm}^2$ (1 MeV neutrons).Comment: 16 pages, 22 figure

Micro-assembly of integrated photonic devices using a high accuracy transfer printing process

This thesis was previously held under moratorium from 03/12/19 to 03/12/21The overall objective of this thesis is the development and implementation of a high accuracy transfer printing (TP) technique for the micro-assembly of integrated photonic devices. The method has particular relevance for the integration of hybrid photonic waveguides, and enables the production of passive/active photonic circuit technologies in a parallel and scalable manner. The initial work involves the design of an optical microscopy based absolute crosscorrelation alignment technique utilised within a custom-built TP system. Following this, the statistical characterisation of the method, with the measured absolute positional accuracy of fully fabricated devices integrated across multiple substrates is achieved. An absolute lateral alignment accuracy of ±385 nm (3σ) and rotational accuracy of ±4.8 mrad (3σ) are demonstrated. This is reported as the highest lateral alignment accuracy to date for transfer printing, lending itself a significant advantage for the micro-assembly of optical waveguiding components. Utilising the high alignment TP system, the micro-assembly of fully fabricated single-mode Si membrane micro-ring resonators on a target silicon-on-insulator (SOI) substrate is presented. The ultra-thin membrane resonators are vertically integrated with Si bus waveguides situated on a receiver SOI chip in a highly controllable manner, demonstrating variation in resonant coupling conditions with respect to the lateral coupling offset. Further to this, the TP method provides a means to produce 3D device architectures without any limiting multi-step full wafer bonding methods. By vertical assembling 3D stacked membrane devices, a 100 µm2 SOI distributed Bragg reflector (DBR) is produced taking advantage of high lateral and rotation placement accuracy. The structure exhibits a visible wavelength reflectance band in agreement with theoretical simulations. The micro-assembly of hybrid AlGaAs-on-SOI micro-disk resonators is also presented, demonstrating the highly controlled integration of pre-fabricated waveguide devices across multiple material platforms. Control over the integrated resonator's vertical and lateral coupling to the bus waveguides enables the precise and selective excitation of different mode families within the resonator cavity. By using the high accuracy TP method, the vertical micro-assembly of hybrid micro-disk resonators also allows selective mode coupling, with loaded Q-factors reaching ~40,000. The unique advantage of the assembled devices however come from the ability to perform (3) nonlinear processes on SOI without being limited by two-photon absorption and free-carrier losses. Four-wave mixing is shown with efficiency levels of -25 dB at a low input power of 2.5 mW, with a nonlinear coeffcient of 325 (Wm)-1 demonstrated. The measured nonlinearity is comparable to its monolithic silicon counterpart, whilst also detailing a clear reduction in the nonlinear losses inherent to this material platform.The overall objective of this thesis is the development and implementation of a high accuracy transfer printing (TP) technique for the micro-assembly of integrated photonic devices. The method has particular relevance for the integration of hybrid photonic waveguides, and enables the production of passive/active photonic circuit technologies in a parallel and scalable manner. The initial work involves the design of an optical microscopy based absolute crosscorrelation alignment technique utilised within a custom-built TP system. Following this, the statistical characterisation of the method, with the measured absolute positional accuracy of fully fabricated devices integrated across multiple substrates is achieved. An absolute lateral alignment accuracy of ±385 nm (3σ) and rotational accuracy of ±4.8 mrad (3σ) are demonstrated. This is reported as the highest lateral alignment accuracy to date for transfer printing, lending itself a significant advantage for the micro-assembly of optical waveguiding components. Utilising the high alignment TP system, the micro-assembly of fully fabricated single-mode Si membrane micro-ring resonators on a target silicon-on-insulator (SOI) substrate is presented. The ultra-thin membrane resonators are vertically integrated with Si bus waveguides situated on a receiver SOI chip in a highly controllable manner, demonstrating variation in resonant coupling conditions with respect to the lateral coupling offset. Further to this, the TP method provides a means to produce 3D device architectures without any limiting multi-step full wafer bonding methods. By vertical assembling 3D stacked membrane devices, a 100 µm2 SOI distributed Bragg reflector (DBR) is produced taking advantage of high lateral and rotation placement accuracy. The structure exhibits a visible wavelength reflectance band in agreement with theoretical simulations. The micro-assembly of hybrid AlGaAs-on-SOI micro-disk resonators is also presented, demonstrating the highly controlled integration of pre-fabricated waveguide devices across multiple material platforms. Control over the integrated resonator's vertical and lateral coupling to the bus waveguides enables the precise and selective excitation of different mode families within the resonator cavity. By using the high accuracy TP method, the vertical micro-assembly of hybrid micro-disk resonators also allows selective mode coupling, with loaded Q-factors reaching ~40,000. The unique advantage of the assembled devices however come from the ability to perform (3) nonlinear processes on SOI without being limited by two-photon absorption and free-carrier losses. Four-wave mixing is shown with efficiency levels of -25 dB at a low input power of 2.5 mW, with a nonlinear coeffcient of 325 (Wm)-1 demonstrated. The measured nonlinearity is comparable to its monolithic silicon counterpart, whilst also detailing a clear reduction in the nonlinear losses inherent to this material platform

Next Generation Silicon Photonic Transceiver: From Device Innovation to System Analysis

Silicon photonics is recognized as a disruptive technology that has the potential to reshape many application areas, for example, data center communication, telecommunications, high-performance computing, and sensing. The key capability that silicon photonics offers is to leverage CMOS-style design, fabrication, and test infrastructure to build compact, energy-efficient, and high-performance integrated photonic systems-on- chip at low cost. As the need to squeeze more data into a given bandwidth and a given footprint increases, silicon photonics becomes more and more promising. This work develops and demonstrates novel devices, methodologies, and architectures to resolve the challenges facing the next-generation silicon photonic transceivers. The first part of this thesis focuses on the topology optimization of passive silicon photonic devices. Specifically, a novel device optimization methodology - particle swarm optimization in conjunction with 3D finite-difference time-domain (FDTD), has been proposed and proven to be an effective way to design a wide range of passive silicon photonic devices. We demonstrate a polarization rotator and a 90◦ optical hybrid for polarization-diversity and phase-diversity communications - two important schemes to increase the communication capacity by increasing the spectral efficiency. The second part of this thesis focuses on the design and characterization of the next- generation silicon photonic transceivers. We demonstrate a polarization-insensitive WDM receiver with an aggregate data rate of 160 Gb/s. This receiver adopts a novel architecture which effectively reduces the polarization-dependent loss. In addition, we demonstrate a III-V/silicon hybrid external cavity laser with a tuning range larger than 60 nm in the C-band on a silicon-on-insulator platform. A III-V semiconductor gain chip is hybridized into the silicon chip by edge-coupling to the silicon chip. The demonstrated packaging method requires only passive alignment and is thus suitable for high-volume production. We also demonstrate all silicon-photonics-based transmission of 34 Gbaud (272 Gb/s) dual-polarization 16-QAM using our integrated laser and silicon photonic coherent transceiver. The results show no additional penalty compared to commercially available narrow linewidth tunable lasers. The last part of this thesis focuses on the chip-scale optical interconnect and presents two different types of reconfigurable memory interconnects for multi-core many-memory computing systems. These reconfigurable interconnects can effectively alleviate the memory access issues, such as non-uniform memory access, and Network-on-Chip (NoC) hot-spots that plague the many-memory computing systems by dynamically directing the available memory bandwidth to the required memory interface

Silicon Photonic Platforms and Systems for High-speed Communications

Data communication is a critical component of modern technology in our society. There is an increasing reliance on information being at our fingers tips and we expect a low-latency, high-bandwidth connection to deliver entertainment or enhanced productivity. In order to serve this demand, communications devices are being pressed for smaller form factors, higher data throughput, lower power consumption and lower cost. Similar demands exist in a number of applications including metro/long-haul telecommunications, shorter datacenter links and supercomputing. Silicon photonics promises to be a technology that will solve some of the difficulties with improving communication devices. Building photonics in silicon allows for reuse of the same fabrication technology that is used by the CMOS electronics industry, potentially allowing for large volumes, high yields and low costs. Part I of this thesis details the design of components needed in a high-speed silicon photonic platform to meet the current challenges for high-speed communications. The author’s work in modeling photodetectors resulted in improving photodetector bandwidth from 30 GHz to 67 GHz, the fastest reported at the time of publication. Details regarding the optimization and test of modulators are also presented with the first-reported 50 Gbps modulator at 1310-nm. A large scale parallel channel demonstration of high-speed silicon photonics is then presented showing the potential scalability for silicon photonics systems. A full transceiver requires a number of components other than the photodetector and modulator that are the core active pieces of a silicon photonics platform. Part II includes work on the design and test of silicon photonic components providing functionality beyond the photodetector and modulator. A novel design integrating Metal-Semiconductor Field Effect Transistors (MESFETs) into a silicon photonics platform without process change is shown. This integration enables enhanced control functionality with minimal overhead. The critical final piece for a silicon photonics platform, adding a light source, is demonstrated along with performance results of the resulting tunable, extended C-band laser. In Part III, previous work on an enhanced silicon photonics platform with complementary components is used to build a high-speed integrated coherent link and then tested with a silicon photonics-based tunable laser. The transceiver was shown to operate at 34 Gbaud dual-polarization 16-QAM for a total of 272 Gbps over a single channel. This was the first published demonstration of an integrated coherent where all of the optics were built in a silicon photonics platform

Analysis, design, and fabrication of an electric induction micromotor for a micro gas-turbine generator

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2001.Includes bibliographical references (p. 223-227).This thesis presents the analysis, design, fabrication, and testing of the first axial-gap electric induction micromotor, and the first controlled measurement of electric micromotor torque using integrated mechanical springs. Electric induction micromotors offer several advantages over electric variable capacitance micromotors and magnetic micromotors: neither rotor position nor speed need be known to achieve good performance; perfect sinusoids can be used for actuation to eliminate switching losses without loss of motor performance. In addition, the motor is fabricated from IC-compatible materials. The tethered motor is a metrology device. To eliminate bearings and all friction forces, the rotor is attached to fixed supports by single-crystal silicon tethers that are calibrated after fabrication. The tethers are relatively compliant in the azimuthal plane, but stiff axially. This enables accurate measurement of in-plane displacements, free from losses, while preventing out-of-plane displacements that would alter the gap. Ideally, the micromotor is fabricated from two fusion-bonded wafers in a process of 189 steps using 13 masks. Process complication comes from several sources. First, the stator structure uses a damascene insulator process to provide very thick passivation. Second, the rotor charge relaxation time constant is adjusted using a moderately Boron-doped polysilicon conductor. Third, tethers are defined by a through-wafer etch to be 385 jim tall and only 8 jim wide. Finally, the stator and rotor wafer are to be fusion bonded at the wafer level, although this was not carried out for the tested motor; it was assembled by hand with epoxy. Torque is measured as high as 0.220 [mu]N-m with 90 V square-wave actuation. Torque is shown to be consistent with models and the torque curves are shown to shift with rotor conductivity as expected with reference to a magnetic induction machine. The measurements are consistent with a gap of 12 [mu]m, which is shown to be a result of the hand-assembly process. Bonding would yield a gap of 3 [mu]m, making torque of 3 [mu]N-m possible at the same voltage.by Steven F. Nagle.Ph.D

Glass multilayer bonding for high density interconnect substrates

The aim of this research was the investigation of bonding borosilicate glass sheets, its trade mark CMZ, 100μm thickness, to create multilayer substrates capable of supporting high-density electrical interconnections. CMZ glass was chosen as it has a coefficient of thermal expansion that is close to that of silicon, thereby minimising thermal stresses in assemblies generated by manufacturing processes or service conditions. Two different methods of bonding the glass were used in this study; pressure assisted low temperature bonding (PALTB), and water glass bonding, using Sodium Trisilicate (Na2Si3O7) solution. These two bonding methods have already been applied in electronics manufacturing applications, such as silicon wafer bonding and multichip modules (MCMs). However, glass-to-glass bonding is a relatively new subject and this study is an attempt to standardise bonding processes. Additionally, the concept of using glass as a multilayer substrate provides a foundation for further exploration by other investigators. Initial tests that were carried out before standardising the procedures for these two methods showed that a two-stage bonding process provided optimum results. A preliminary stage commenced by placing the cleaned (using Decon 90 solution) samples in a vacuum oven for 15 minutes, then heating at 100oC for 1hr. The permanent stage was then achieved by heating the samples in a conventional oven at temperatures from 200 to 400oC, for different periods. At this stage, the main difference between the two methods was the application of pressure (1-2MPa) during heating of the PALTB samples. To evaluate the quality of the bonds, qualitative tests such as visual, optical microscope and dye penetrant were used. In addition, to estimate the strength and the rigidity of the interlayer bonds, two quantitative tests, comprising of deflection under cyclic stresses and crack opening were used. Thermal cycling and humidity tests were also used to assess resistance of the bonds to environmental effects. The results showed that heating to 100oC was insufficient to enhance the bonds, as occasionally a sudden increase of deflection was observed indicating slippage/delamination. These bonds were enhanced during the permanent bonding stage by heating to 300oC in PALTB, under a pressure of 1-2MPa. The crack-opening test showed that the delamination distances of the bonds in the permanent stage were lower than that for preliminary bonding in both bonding methods. The delamination distances from the crack opening tests were used to calculate the strain energy release rate (GIC) and fracture toughness (KIC) values of the interlayers. The results showed that the KIC values of the permanent PALTB and water glass interlayers were higher than 1MPa.m0.5, while the KIC value of the CMZ glass, determined by linear elastic fracture mechanics, was around 0.8MPa.m0.5. The optical observations revealed that the prepared bonded sheets did not delaminate or break after thermal cycling and humidity tests