Nonexistence Certificates for Ovals in a Projective Plane of Order Ten

In 1983, a computer search was performed for ovals in a projective plane of order ten. The search was exhaustive and negative, implying that such ovals do not exist. However, no nonexistence certificates were produced by this search, and to the best of our knowledge the search has never been independently verified. In this paper, we rerun the search for ovals in a projective plane of order ten and produce a collection of nonexistence certificates that, when taken together, imply that such ovals do not exist. Our search program uses the cube-and-conquer paradigm from the field of satisfiability (SAT) checking, coupled with a programmatic SAT solver and the nauty symbolic computation library for removing symmetries from the search.Comment: Appears in the Proceedings of the 31st International Workshop on Combinatorial Algorithms (IWOCA 2020

Proceedings of the 21st Conference on Formal Methods in Computer-Aided Design – FMCAD 2021

The Conference on Formal Methods in Computer-Aided Design (FMCAD) is an annual conference on the theory and applications of formal methods in hardware and system verification. FMCAD provides a leading forum to researchers in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing

Proceedings of Formal Methods in Computer-Aided Design, FMCAD 2019

Table of Contents: Boosting Verification Scalability via Structural Grouping and Semantic Partitioning of Properties / by Rohit Dureja, Jason Baumgartner, Alexander Ivrii, Robert Kanzelman and Kristin Yvonne Rozier (p. 1) -- Input Elimination Transformations for Scalable Verification and Trace Reconstruction / by Raj Kumar Gajavelly, Jason Baumgartner, Alexander Ivrii, Robert Kanzelman and Shiladitya Ghosh (p. 10) -- Chasing Minimal Inductive Validity Cores in Hardware Model Checking / by Ryan Berryhill and Andreas Veneris (p. 19) -- Verifying Large Multipliers by Combining SAT and Computer Algebra / by Daniela Kaufmann, Armin Biere and Manuel Kauers (p. 28) -- Unification-based Pointer Analysis without Oversharing / by Jakub Kuderski, Jorge A. Navas and Arie Gurfinkel (p. 37) -- Concurrent Chaining Hash Maps for Software Model Checking / by Freark I. van der Berg and Jaco van de Pol (p. 46) -- Proving Data Race Freedom in Task Parallel Programs with a Weaker Partial Order / by Benjamin Ogles, Peter Aldous and Eric Mercer (p. 55) -- BDD-Based Algorithms for Packet Classification / by Nina Narodytska, Leonid Ryzhyk, Igor Ganichev and Soner Sevinc (p. 64) -- TSNsched: Automated Schedule Generation for Time Sensitive Networking / by Aellison Cassimiro Teixeira Dos Santos, Ben Schneider and Vivek Nigam (p. 69) -- Verification and Synthesis of Symmetric Uni-Rings for Leads-To Properties / by Ali Ebnenasir (p. 78) -- Scalable Translation Validation of Unverified Legacy OS Code / by Amer Tahat, Sarang Joshi, Pronnoy Goswami and Binoy Ravindran (p. 87) -- Kaizen: Building a Performant Blockchain System Verified for Consensus and Integrity / by Faria Kalim, Karl Palmskog, Jayasi Mehar, Adithya Murali, Indranil Gupta and P. Madhusudan (p. 96) -- KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design / by Luca Piccolboni, Giuseppe Di Guglielmo and Luca Carloni (p. 105) -- Verification of Authenticated Firmware Loaders / by Sujit Kumar Muduli, Pramod Subramanyan and Sayak Ray (p. 110) -- Learning-Based Synthesis of Safety Controllers / by Daniel Neider and Oliver Markgraf (p. 120) -- Shield Synthesis for Real: Enforcing Safety in Cyber-Physical Systems / by Meng Wu, Jingbo Wang, Jyotirmoy Deshmukh and Chao Wang (p. 129) -- Syntroids: Synthesizing a Game for FPGAs using Temporal Logic Specifications / by Gideon Geier, Philippe Heim, Felix Klein and Bernd Finkbeiner (p. 138) -- Synthesizing Reactive Systems Using a Robustness Specification / by Roderick Bloem, Hana Chockler, Masoud Ebrahimi and Ofer Strichman (p. 147) -- Property Directed Inference of Relational Invariants / by Dmitry Mordvinov and Grigory Fedyukovich (p. 152) -- Knowledge Compilation for Boolean Functional Synthesis / by S. Akshay, Jatin Arora, Supratik Chakraborty, Krishna S, Divya Raghunathan and Shetal Shah (p. 161) -- Verifying Relational Properties using Trace Logic / by Gilles Barthe, Renate Eilers, Pamina Georgiou, Bernhard Gleiss, Laura Kovacs and Matteo Maffei (p. 170) -- Autarkies for DQCNF / by Oliver Kullmann and Ankit Shukla (p. 179) -- Localizing Quantifiers for DQBF / by Aile Ge-Ernst, Christoph Scholl and Ralf Wimmer (p. 184) -- Anytime Weighted MaxSAT with Improved Polarity Selection and Bit-Vector Optimization / by Alexander Nadel (p. 193) -- GuidedSampler: Coverage-guided Sampling of SMT Solutions / by Rafael Dutra, Jonathan Bachrach and Koushik Sen (p. 203) -- Extending enumerative function synthesis via SMT-driven classification / by Haniel Barbosa, Andrew Reynolds, Daniel Larraz and Cesare Tinelli (p. 212) -- Proving Non-Termination via Loop Acceleration / by Florian Frohn and Jürgen Giesl (p. 221)Computer Science