Design and application of reconfigurable circuits and systems

Open Acces

Online Timing Slack Measurement and its Application in Field-Programmable Gate Arrays

Reliability, power consumption and timing performance are key concerns for today's integrated circuits. Measurement techniques capable of quantifying the timing characteristics of a circuit, while it is operating, facilitate a range of benefits. Delay variation due to environmental and operational conditions, and degradation can be monitored by tracking changes in timing performance. Using the measurements in a closed-loop to control power supply voltage or clock frequency allows for the reduction of timing safety margins, leading to improvements in power consumption or throughput performance through the exploitation of better-than worst-case operation. This thesis describes a novel online timing slack measurement method which can directly measure the timing performance of a circuit, accurately and with minimal overhead. Enhancements allow for the improvement of absolute accuracy and resolution. A compilation flow is reported that can automatically instrument arbitrary circuits on FPGAs with the measurement circuitry. On its own this measurement method is able to track the "health" of an integrated circuit, from commissioning through its lifetime, warning of impending failure or instigating pre-emptive degradation mitigation techniques. The use of the measurement method in a closed-loop dynamic voltage and frequency scaling scheme has been demonstrated, achieving significant improvements in power consumption and throughput performance.Open Acces

Spéculation temporelle pour accélérateurs matériels

This thesis is focused on the use of timing speculation to improve the performance and energy efficiency of hardware accelerators. Timing speculation is the use of a circuit using a frequency or a voltage at which its operation is no longer guaranteed. It increases the performance of the circuit (computations per second) but also its energy efficiency (computations per joule). As the correct operation of the circuit is no longer guaranteed, it must be accompanied by an error detection mechanism. This mechanism must have the lowest possible additional cost in terms of resources used, energy and impact on performance. These overheads must indeed be low enough to make the approach worthwhile, but also be as low as possible to maximize the gain obtained. We present a new algorithm-level error detection mechanism for convolutions used in convolutional neural networks that meets these conditions. We show that combining this mechanism with timing speculation can improve the performance and energy efficiency of a convolution hardware accelerator.Résumé : Cette thèse porte sur l’utilisation de la spéculation temporelle pour améliorer les performances et l’efficacité énergétique d’accélérateurs matériels. La spéculation temporelle consiste en l’utilisation d’un circuit en utilisant une fréquence ou une tension à laquelle son fonctionnement n’est plus garanti. Elle permet d’augmenter les performances du circuit (calculs par seconde) mais aussi son efficacité énergétique (calculs par joule). Comme le fonctionnement du circuit n’est plus garanti, elle doit être accompagnée d’un mécanisme de détection d’erreur. Celui-ci doit avoir un coût en ressources utilisées, en énergie et un impact sur les performances les plus faibles possibles. Ces surcoûts doivent effectivement être suffisamment faibles pour que l’approche vaille le coup, mais aussi être le plus bas possible pour maximiser les gains obtenus. Nous présentons un nouveau mécanisme de détection d’erreur au niveau algorithmique pour les convolutions utilisées dans les réseaux de neurones convolutifs qui remplit ces conditions. Nous montrons que la combinaison de ce mécanisme avec la spéculation temporelle permet d’améliorer les performances et l’efficacité énergétique d’un accélérateur matériel de convolution