Ultra high speed image processing techniques

Packaging techniques for ultra high speed image processing were developed. These techniques involve the development of a signal feedthrough technique through LSI/VLSI sapphire substrates. This allows the stacking of LSI/VLSI circuit substrates in a 3 dimensional package with greatly reduced length of interconnecting lines between the LSI/VLSI circuits. The reduced parasitic capacitances results in higher LSI/VLSI computational speeds at significantly reduced power consumption levels

A procedural method for the efficient implementation of full-custom VLSI designs

An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system

From Microelectronics to Nanoelectronics: Introducing Nanotechnology to VLSI Curricula

© 2011 by ASEEIn the past decades, VLSI industries constantly shrank the size of transistors, so that more and more transistors can be built into the same chip area to make VLSI more and more powerful in its functions. As the typical feature size of CMOS VLSI is shrunk into deep submicron domain, nanotechnology is the next step in order to maintain Moore’s law for several more decades. Nanotechnology not only further improves the resolution in traditional photolithography process, but also introduces many brand-new fabrication strategies, such as bottom-up molecular self-assembly. Nanotechnology is also enabling many novel devices and circuit architectures which are totally different from current microelectronics circuits, such as quantum computing, nanowire crossbar circuits, spin electronics, etc. Nanotechnology is bringing another technology revolution to traditional CMOS VLSI technology. In order to train students to meet the quickly-increasing industry demand for nextgeneration nanoelectronics engineers, we are making efforts to introduce nanotechnology into our VLSI curricula. We have developed a series of VLSI curricula which include CPE/EE 448D - Introduction to VLSI, EE 548 - Low Power VLSI Circuit Design, EE 458 - Analog VLSI Circuit Design, EE 549 - VLSI Testing, etc. Furthermore, we developed a series of micro and nanotechnology related courses, such as EE 451 - Nanotechnology, EE 448 - Microelectronic Fabrication, EE 446 – MEMS (Microelectromechanical Systems). We introduce nanotechnology into our VLSI curricula, and teach the students about various devices, fabrication processes, circuit architectures, design and simulation skills for future nanotechnology-based nanoelectronic circuits. Some examples are nanowire crossbar circuit architecture, carbon-nanotube based nanotransistor, single-electron transistor, spintronics, quantum computing, bioelectronic circuits, etc. Students show intense interest in these exciting topics. Some students also choose nanoelectronics as the topic for their master project/thesis, and perform successful research in the field. The program has attracted many graduate students into the field of nanoelectronics

Parallel VLSI architecture emulation and the organization of APSA/MPP

The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms

Direct measurement of the on-chip insertion loss of high finesse microring resonators in Si3N4-SiO2 technology.

Microring resonators show the possibility for designing Very Large Scale Integrated (VLSI) photonic circuits by cascading them. In order to realize the devices, the on-chip insertion loss becomes an important parameter. The direct measurement of the on-chip insertion loss of a high finesse microring resonator will be presented. Its value (0.1 ± 0.1) dB is low, in agreement with calculations