Real-time and fault tolerance in distributed control software

Closed loop control systems typically contain multitude of spatially distributed sensors and actuators operated simultaneously. So those systems are parallel and distributed in their essence. But mapping this parallelism onto the given distributed hardware architecture, brings in some additional requirements: safe multithreading, optimal process allocation, real-time scheduling of bus and network resources. Nowadays, fault tolerance methods and fast even online reconfiguration are becoming increasingly important. All those often conflicting requirements, make design and implementation of real-time distributed control systems an extremely difficult task, that requires substantial knowledge in several areas of control and computer science. Although many design methods have been proposed so far, none of them had succeeded to cover all important aspects of the problem at hand. [1] Continuous increase of production in embedded market, makes a simple and natural design methodology for real-time systems needed more then ever

Efficient Memory-Protected Integration of Add-On Software Subsystems in Small Embedded Automotive Applications

Current innovations in the automotive industry evolve mainly in the electronics and software domain. This leads to an increasing integration of additional software subsystems into already existing electronic control units (ECUs) to cope with the raised amount and complexity of present ECUs in modern high-end vehicles. This paper discusses different approaches which are required to integrate such add-on software subsystems in an isolated memory domain, and considers particularly the special needs of small embedded systems—including the limited hardware support. Special focus is brought to the efficient detection of malicious memory accesses, as well as the benefits of a thereupon possible and adaptable failure-handling strategy. All investigations are based on a developed memory-protection framework which has been tailored to the special needs of a sample vehicle dynamics control system. Its usage allows the combination of. integrating additional subsystems without reducing the main application’s availability

Programming MPSoC platforms: Road works ahead

This paper summarizes a special session on multicore/multi-processor system-on-chip (MPSoC) programming challenges. The current trend towards MPSoC platforms in most computing domains does not only mean a radical change in computer architecture. Even more important from a SW developer´s viewpoint, at the same time the classical sequential von Neumann programming model needs to be overcome. Efficient utilization of the MPSoC HW resources demands for radically new models and corresponding SW development tools, capable of exploiting the available parallelism and guaranteeing bug-free parallel SW. While several standards are established in the high-performance computing domain (e.g. OpenMP), it is clear that more innovations are required for successful\ud deployment of heterogeneous embedded MPSoC. On the other hand, at least for coming years, the freedom for disruptive programming technologies is limited by the huge amount of certified sequential code that demands for a more pragmatic, gradual tool and code replacement strategy

Human-computer cooperation platform for developing real-time robotic applications

[EN] This paper presents a human-computer cooperation platform, which permits the coordination between the user and the tool to improve the development of real-time control applications (e.g., mobile robots). These applications have functional (robot objectives) and temporal requirements to accomplish (deadlines guarantee of tasks). The simulation tool has been designed in order to permit the testing and validation of these two requirements. To this end, the tool is composed of two independent simulators interconnected through a shared memory: the robot simulator (functional level) and the real-time task scheduler simulator (task execution level). Robotic applications can be defined with the robot simulator while the real-time scheduler simulator permits to analyze the schedulability of the robotic tasks. The real-time task simulator incorporates a flexible task model where the task temporal parameters (e.g., computation time) adapt to the requirements of the application (e.g., number of objects in scenes); thus, the use of the CPU is not overestimated. A key issue of the framework is the human-computer interface, which allows the monitoring of different parameters of the application: robot objectives, task schedule, robot speed, computation time, CPU utilization, deadline misses. The usefulness of the simulation tool is shown through different robotic navigation experiments. Finally, the simulation tool has been used to evaluate the proposed flexible model of tasks compared to a traditional fixed temporal parameters task model. Results show that the robot fulfills the objectives earlier, about 32% on average, and consumes on average about 15% less CPU to accomplish the objectives.Domínguez Montagud, CP.; Martínez-Rubio, J.; Busquets Mataix, JV.; Hassan Mohamed, H. (2019). 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Supporting Read/Write Applications in Embedded Real-time Systems via Suspension-aware Analysis

In many embedded real-time systems, applications often interact with I/O devices via read/write operations, which may incur considerable suspension delays. Unfortunately, prior analysis methods for validating timing correctness in embedded systems become quite pessimistic when suspension delays are present. In this paper, we consider the problem of supporting two common types of I/O applications in a multiprocessor system, that is, write-only applications and read-write applications. For the write-only application model, we present a much improved analysis technique that results in only O(m) suspension-related utilization loss, where m is the number of processors. For the second application model, we present a flexible I/O placement strategy and a corresponding new scheduling algorithm, which can completely circumvent the negative impact due to read- and write-induced suspension delays. We illustrate the feasibility of the proposed I/O-placement-based schedule via a case study implementation. Furthermore, experiments presented herein show that the improvement with respect to system utilization over prior methods is often significant

Formal and Informal Methods for Multi-Core Design Space Exploration

We propose a tool-supported methodology for design-space exploration for embedded systems. It provides means to define high-level models of applications and multi-processor architectures and evaluate the performance of different deployment (mapping, scheduling) strategies while taking uncertainty into account. We argue that this extension of the scope of formal verification is important for the viability of the domain.Comment: In Proceedings QAPL 2014, arXiv:1406.156