Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits

In this paper, the analog/mixed-signal performance is evaluated at device and circuit levels for a III-V nanowire tunnel field effect transistor (TFET) technology platform and compared against the predictive model for FinFETs at the 10-nm technology node. The advantages and limits of TFETs over their FinFET counterparts are discussed in detail, considering the main analog figures of merits, as well as the implementation of low-voltage track and-hold (T/H) and comparator circuits. It is found that the higher output resistance offered by TFET-based designs allows achieving significantly higher intrinsic voltage gain and higher maximum-oscillation frequency at low current levels. TFET-based T/H circuits have better accuracy and better hold performance by using the dummy switch solution for the mitigation of the charge injection. Among the comparator circuits, the TFET-based conventional dynamic architecture exhibits the best performance while keeping lower area occupation with respect to the more complex double-tail circuits. Moreover, it outperforms all the FinFET counterparts over a wide range of supply voltage when considering low values of the common-mode voltage

Understanding the basic advantages of bulk FinFETs for sub- and near-threshold logic circuits from device measurements

This study aims to understand the potential of bulk FinFET technology from the perspective of sub- and near-threshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high-k/metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub- and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements

This study aims to understand the potential of bulk FinFET technology from the perspective of sub-and near-threshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high-k/metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub-and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy