3,897 research outputs found
Spin-Based Neuron Model with Domain Wall Magnets as Synapse
We present artificial neural network design using spin devices that achieves
ultra low voltage operation, low power consumption, high speed, and high
integration density. We employ spin torque switched nano-magnets for modelling
neuron and domain wall magnets for compact, programmable synapses. The spin
based neuron-synapse units operate locally at ultra low supply voltage of 30mV
resulting in low computation power. CMOS based inter-neuron communication is
employed to realize network-level functionality. We corroborate circuit
operation with physics based models developed for the spin devices. Simulation
results for character recognition as a benchmark application shows 95% lower
power consumption as compared to 45nm CMOS design
Design of Adiabatic MTJ-CMOS Hybrid Circuits
Low-power designs are a necessity with the increasing demand of portable
devices which are battery operated. In many of such devices the operational
speed is not as important as battery life. Logic-in-memory structures using
nano-devices and adiabatic designs are two methods to reduce the static and
dynamic power consumption respectively. Magnetic tunnel junction (MTJ) is an
emerging technology which has many advantages when used in logic-in-memory
structures in conjunction with CMOS. In this paper, we introduce a novel
adiabatic hybrid MTJ/CMOS structure which is used to design AND/NAND, XOR/XNOR
and 1-bit full adder circuits. We simulate the designs using HSPICE with 32nm
CMOS technology and compared it with a non-adiabatic hybrid MTJ/CMOS circuits.
The proposed adiabatic MTJ/CMOS full adder design has more than 7 times lower
power consumtion compared to the previous MTJ/CMOS full adder
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
Large-capacity Content Addressable Memory (CAM) is a key element in a wide
variety of applications. The inevitable complexities of scaling MOS transistors
introduce a major challenge in the realization of such systems. Convergence of
disparate technologies, which are compatible with CMOS processing, may allow
extension of Moore's Law for a few more years. This paper provides a new
approach towards the design and modeling of Memristor (Memory resistor) based
Content Addressable Memory (MCAM) using a combination of memristor MOS devices
to form the core of a memory/compare logic cell that forms the building block
of the CAM architecture. The non-volatile characteristic and the nanoscale
geometry together with compatibility of the memristor with CMOS processing
technology increases the packing density, provides for new approaches towards
power management through disabling CAM blocks without loss of stored data,
reduces power dissipation, and has scope for speed improvement as the
technology matures.Comment: 10 pages, 11 figure
- …