Digital signal processing block and synchronizer for a sensor microcircuit

Tässä diplomityössä suunniteltiin ja toteutettiin tutkimuskäyttöön tarkoitetulle, kaksiakseliselle kiihtyvyysanturipiirille digitaaliset lohkot, joihin kuului kaksi desimoivaa CIC-suodatinta, SPI-tiedonsiirtoväylä, muistirekisterit säätöbittejä varten, tasapoikkeaman- ja vahvistuksenkorjaimet kiihtyvyyslukemille sekä synkronoija. Piirin AD-muuntimilta saadaan kahden akselin kiihtyvyyksien suuruus yksibittisenä digitaalisena datana. Desimointisuodattimet kasvattavat datan sananleveyttä, suodattavat sitä ja pienentävät sen näytteistystaajuutta. Vaatimuksena oli, ettei kiihtyvyysdatan signaali-kohinasuhde saa pienentyä merkittävästi laskostumisen takia. SPI-väylällä puolestaan mahdollistettiin analogisten ja digitaalisten lohkojen toimintaa säätävien bittien syöttäminen piirille ja digitaalisen kiihtyvyysdatan lukeminen ulkoisen lukijan, esimerkiksi mikrokontrollerin tai tietokoneen, avulla. Kiihtyvyyslukeman tasapoikkeaman ja vahvistuksen korjauksella saadaan pienennettyä piiriyksilöiden antamien kiihtyvyyslukemien välisiä eroja ja synkronoijalla vähennetään merkittävästi asynkronisesta kiihtyvyysdatan lukemisesta aiheutuvia lukemavirheitä. AD-muuntimilta tulevan kiihtyvyysdatan näytteistystaajuus on 100 kHz ja CIC-suodattimet pudottavat sen 100 Hz:iin. Molempien CIC-suodattimien lähdössä sananleveys on 31 bittiä, joka lyhennetään 24-bittiseksi ennen poikkeaman ja vahvistuksen korjaamista. Digitaalilohkot toteutettiin 0,35 um:n CMOS-teknologialla ja niiden käyttöjännite on 3,3 V. Digitaalisolujen käyttämä kokonaispinta-ala on 0,60 mm^2 ja lohkojen kokonaisvirrankulutus on 12 uA, kun molempien akselien 24-bittisiä kiihtyvyysarvoja luetaan SPI-väylän kautta nopeudella 100 näytettä per sekunti.In this Master's thesis, digital integrated circuit blocks were designed and processed for an integrated 2-axis accelerometer microcircuit for a research project. Implemented blocks consist of two decimating CIC filters, an SPI communication interface, memory registers for control bits, a synchronizer and adders and a shared multiplier for correcting the offset and gain of the acceleration outputs. The analog-to-digital converters of the accelerometer system produce 1-bit output data streams. The CIC filters increase the word lengths of the data, filter the noise and decrease the sampling rates. The SPI interface enables writing and reading of control bits for the analog and digital blocks and reading of the acceleration data e.g. with a microcontroller. By using the offset and gain correction, variation of outputs of a set of multiple accelerometer circuits can be decreased. The synchronizer significantly decreases the probability of occurrence of erroneous acceleration values received by an SPI master device when acceleration data is read through the SPI interface asynchronously. Sampling frequency of the 1-bit data from the analog-to-digital converters is 100 kHz. The CIC filters decrease the sampling frequency to 100 Hz and increase the word lengths to 31 bits. The word lengths are truncated to 24 bits and the offsets and gains are corrected by the adders and the shared Booth multiplier. The accelerometer system with the digital block was processed in a 0.35 um CMOS process, whose nominal supply voltage is 3.3 V. The area of the digital core is 0.60 mm^2. Current consumption of the implemented digital blocks is 12 uA, when CIC filters are running and all 24 acceleration data bits of both axes are read at the speed of 100 samples per second

Design and Implementation of Complexity Reduced Digital Signal Processors for Low Power Biomedical Applications

Wearable health monitoring systems can provide remote care with supervised, inde-pendent living which are capable of signal sensing, acquisition, local processing and transmission. A generic biopotential signal (such as Electrocardiogram (ECG), and Electroencephalogram (EEG)) processing platform consists of four main functional components. The signals acquired by the electrodes are amplified and preconditioned by the (1) Analog-Front-End (AFE) which are then digitized via the (2) Analog-to-Digital Converter (ADC) for further processing. The local digital signal processing is usually handled by a custom designed (3) Digital Signal Processor (DSP) which is responsible for either anyone or combination of signal processing algorithms such as noise detection, noise/artefact removal, feature extraction, classification and compres-sion. The digitally processed data is then transmitted via the (4) transmitter which is renown as the most power hungry block in the complete platform. All the afore-mentioned components of the wearable systems are required to be designed and fitted into an integrated system where the area and the power requirements are stringent. Therefore, hardware complexity and power dissipation of each functional component are crucial aspects while designing and implementing a wearable monitoring platform. The work undertaken focuses on reducing the hardware complexity of a biosignal DSP and presents low hardware complexity solutions that can be employed in the aforemen-tioned wearable platforms. A typical state-of-the-art system utilizes Sigma Delta (Σ∆) ADCs incorporating a Σ∆ modulator and a decimation filter whereas the state-of-the-art decimation filters employ linear phase Finite-Impulse-Response (FIR) filters with high orders that in-crease the hardware complexity [1–5]. In this thesis, the novel use of minimum phase Infinite-Impulse-Response (IIR) decimators is proposed where the hardware complexity is massively reduced compared to the conventional FIR decimators. In addition, the non-linear phase effects of these filters are also investigated since phase non-linearity may distort the time domain representation of the signal being filtered which is un-desirable effect for biopotential signals especially when the fiducial characteristics carry diagnostic importance. In the case of ECG monitoring systems the effect of the IIR filter phase non-linearity is minimal which does not affect the diagnostic accuracy of the signals. The work undertaken also proposes two methods for reducing the hardware complexity of the popular biosignal processing tool, Discrete Wavelet Transform (DWT). General purpose multipliers are known to be hardware and power hungry in terms of the number of addition operations or their underlying building blocks like full adders or half adders required. Higher number of adders leads to an increase in the power consumption which is directly proportional to the clock frequency, supply voltage, switching activity and the resources utilized. A typical Field-Programmable-Gate-Array’s (FPGA) resources are Look-up Tables (LUTs) whereas a custom Digital Signal Processor’s (DSP) are gate-level cells of standard cell libraries that are used to build adders [6]. One of the proposed methods is the replacement of the hardware and power hungry general pur-pose multipliers and the coefficient memories with reconfigurable multiplier blocks that are composed of simple shift-add networks and multiplexers. This method substantially reduces the resource utilization as well as the power consumption of the system. The second proposed method is the design and implementation of the DWT filter banks using IIR filters which employ less number of arithmetic operations compared to the state-of-the-art FIR wavelets. This reduces the hardware complexity of the analysis filter bank of the DWT and can be employed in applications where the reconstruction is not required. However, the synthesis filter bank for the IIR wavelet transform has a higher computational complexity compared to the conventional FIR wavelet synthesis filter banks since re-indexing of the filtered data sequence is required that can only be achieved via the use of extra registers. Therefore, this led to the proposal of a novel design which replaces the complex IIR based synthesis filter banks with FIR fil-ters which are the approximations of the associated IIR filters. Finally, a comparative study is presented where the hybrid IIR/FIR and FIR/FIR wavelet filter banks are de-ployed in a typical noise reduction scenario using the wavelet thresholding techniques. It is concluded that the proposed hybrid IIR/FIR wavelet filter banks provide better denoising performance, reduced computational complexity and power consumption in comparison to their IIR/IIR and FIR/FIR counterparts

Phase readout for satellite interferometry

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Applications of MATLAB in Science and Engineering

The book consists of 24 chapters illustrating a wide range of areas where MATLAB tools are applied. These areas include mathematics, physics, chemistry and chemical engineering, mechanical engineering, biological (molecular biology) and medical sciences, communication and control systems, digital signal, image and video processing, system modeling and simulation. Many interesting problems have been included throughout the book, and its contents will be beneficial for students and professionals in wide areas of interest