1,598 research outputs found
A Reduced Latency List Decoding Algorithm for Polar Codes
Long polar codes can achieve the capacity of arbitrary binary-input discrete
memoryless channels under a low complexity successive cancelation (SC) decoding
algorithm. But for polar codes with short and moderate code length, the
decoding performance of the SC decoding algorithm is inferior. The cyclic
redundancy check (CRC) aided successive cancelation list (SCL) decoding
algorithm has better error performance than the SC decoding algorithm for short
or moderate polar codes. However, the CRC aided SCL (CA-SCL) decoding algorithm
still suffer from long decoding latency. In this paper, a reduced latency list
decoding (RLLD) algorithm for polar codes is proposed. For the proposed RLLD
algorithm, all rate-0 nodes and part of rate-1 nodes are decoded instantly
without traversing the corresponding subtree. A list maximum-likelihood
decoding (LMLD) algorithm is proposed to decode the maximum likelihood (ML)
nodes and the remaining rate-1 nodes. Moreover, a simplified LMLD (SLMLD)
algorithm is also proposed to reduce the computational complexity of the LMLD
algorithm. Suppose a partial parallel list decoder architecture with list size
is used, for an (8192, 4096) polar code, the proposed RLLD algorithm can
reduce the number of decoding clock cycles and decoding latency by 6.97 and
6.77 times, respectively.Comment: 7 pages, accepted by 2014 IEEE International Workshop on Signal
Processing Systems (SiPS
Rate-Flexible Fast Polar Decoders
Polar codes have gained extensive attention during the past few years and
recently they have been selected for the next generation of wireless
communications standards (5G). Successive-cancellation-based (SC-based)
decoders, such as SC list (SCL) and SC flip (SCF), provide a reasonable error
performance for polar codes at the cost of low decoding speed. Fast SC-based
decoders, such as Fast-SSC, Fast-SSCL, and Fast-SSCF, identify the special
constituent codes in a polar code graph off-line, produce a list of operations,
store the list in memory, and feed the list to the decoder to decode the
constituent codes in order efficiently, thus increasing the decoding speed.
However, the list of operations is dependent on the code rate and as the rate
changes, a new list is produced, making fast SC-based decoders not
rate-flexible. In this paper, we propose a completely rate-flexible fast
SC-based decoder by creating the list of operations directly in hardware, with
low implementation complexity. We further propose a hardware architecture
implementing the proposed method and show that the area occupation of the
rate-flexible fast SC-based decoder in this paper is only of the total
area of the memory-based base-line decoder when 5G code rates are supported
Successive Cancellation List Polar Decoder using Log-likelihood Ratios
Successive cancellation list (SCL) decoding algorithm is a powerful method
that can help polar codes achieve excellent error-correcting performance.
However, the current SCL algorithm and decoders are based on likelihood or
log-likelihood forms, which render high hardware complexity. In this paper, we
propose a log-likelihood-ratio (LLR)-based SCL (LLR-SCL) decoding algorithm,
which only needs half the computation and storage complexity than the
conventional one. Then, based on the proposed algorithm, we develop
low-complexity VLSI architectures for LLR-SCL decoders. Analysis results show
that the proposed LLR-SCL decoder achieves 50% reduction in hardware and 98%
improvement in hardware efficiency.Comment: accepted by 2014 Asilomar Conference on Signals, Systems, and
Computer
A Multi-Kernel Multi-Code Polar Decoder Architecture
Polar codes have received increasing attention in the past decade, and have
been selected for the next generation of wireless communication standard. Most
research on polar codes has focused on codes constructed from a
polarization matrix, called binary kernel: codes constructed from binary
kernels have code lengths that are bound to powers of . A few recent works
have proposed construction methods based on multiple kernels of different
dimensions, not only binary ones, allowing code lengths different from powers
of . In this work, we design and implement the first multi-kernel successive
cancellation polar code decoder in literature. It can decode any code
constructed with binary and ternary kernels: the architecture, sized for a
maximum code length , is fully flexible in terms of code length, code
rate and kernel sequence. The decoder can achieve frequency of more than
GHz in nm CMOS technology, and a throughput of Mb/s. The area
occupation ranges between mm for and mm for
. Implementation results show an unprecedented degree of
flexibility: with , up to code lengths can be decoded with
the same hardware, along with any kernel sequence and code rate
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