Exploring the Mysteries of System-Level Test

System-level test, or SLT, is an increasingly important process step in today's integrated circuit testing flows. Broadly speaking, SLT aims at executing functional workloads in operational modes. In this paper, we consolidate available knowledge about what SLT is precisely and why it is used despite its considerable costs and complexities. We discuss the types or failures covered by SLT, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT. Observing that the theoretical understanding for all these questions has not yet reached the level of maturity of the more conventional structural and functional test methods, we outline new and promising directions for methodical developments leveraging on recent findings from software engineering.Comment: 7 pages, 2 figure

The role of the pediatrican in the effort to prevent congenital malformations

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Delay test for diagnosis of power switches

Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosingpower switches. The proposed diagnosis method utilizes recently proposed DFT solution for efficient testing of power switches in the presence of PVT variation. It divides power switches into segments such that any faulty power switch is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; and the worst case loss of accuracy is less than 12% when considering VT (Voltage and Temperature) variations

Fault modelling and accelerated simulation of integrated circuits manufacturing defects under process variation

As silicon manufacturing process scales to and beyond the 65-nm node, process variation can no longer be ignored. The impact of process variation on integrated circuit performance and power has received significant research input. Variation-aware test, on the other hand, is a relatively new research area that is currently receiving attention worldwide.Research has shown that test without considering process variation may lead to loss of test quality. Fault modelling and simulation serve as a backbone of manufacturing test. This thesis is concerned with developing efficient fault modelling techniques and simulation methodologies that take into account the effect of process variation on manufacturing defects with particular emphasis on resistive bridges and resistive opens.The first contribution of this thesis addresses the problem of long computation time required to generate logic fault of resistive bridges under process variation by developing a fast and accurate modelling technique to model logic fault behaviour of resistive bridges.The new technique is implemented by employing two efficient voltage calculation algorithms to calculate the logic threshold voltage of driven gates and critical resistance of a fault-site to enable the computation of bridge logic faults without using SPICE. Simulation results show that the technique is fast (on average 53 times faster) and accurate (worst case is 2.64% error) when compared with HSPICE. The second contribution analyses the complexity of delay fault simulation of resistive bridges to reduce the computation time of delay fault when considering process variation. An accelerated delay fault simulation methodology of resistive bridges is developed by employing a three-step strategy to speed up the calculation of transient gate output voltage which is needed to accurately compute delay faults. Simulation results show that the methodology is on average 17.4 times faster, with 5.2% error in accuracy, when compared with HSPICE. The final contribution presents an accelerated simulation methodology of resistive opens to address the problem of long simulation time of delay fault when considering process variation. The methodology is implemented by using two efficient algorithms to accelerate the computation of transient gate output voltage and timing critical resistance of an open fault-site. Simulation results show that the methodology is on average up to 52 times faster than HSPICE, with 4.2% error in accuracy

Special session: Hot topics: Statistical test methods

International audienceThe process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.Advanced statistical data processing offers a powerful set of tools, borrowed from the fields of data mining, machine learning or artificial intelligence, to get the most out of this data. Indeed, these mathematical tools have opened a number of novel and interesting research lines within the field of IC testing.In this special session, prominent researchers in this field will share their views on this topic and present some of their last findings. The first talk will discuss the interest of likelihood prevalence in random fault simulation. The second talk will show how statistical data analysis can help diagnosing test efficiency. The third talk will deal with the reliability of Alternate Test of AMS-RF circuits. The fourth and last talk will address the idea of mining the test data for improving design manufacturing and even test itself

Fetal Alcohol Syndrome: Physical Therapy Implications and Treatment Strategies

Fetal Alcohol Syndrome (FAS) describes physical and neurological (motor, cognitive, and behavioral) deficits that result from maternal alcohol intake during pregnancy. FAS is the leading cause of mental retardation and birth defects in the U.S., ahead of spina bifida, fragile X syndrome, and down\u27s syndrome. The incidence of FAS increased more than three-fold from 1979 to 1992; this increasing incidence rate, enhances the importance of the Physical Therapists\u27 role in early recognition and intervention of FAS. A review of current F AS research studies, reveals a need for additional resource information on FAS, regarding implications for Physical Therapy and possible treatment strategies. The purpose of this independent study is to create an organized resource, specific to Physical Therapists, that includes the diagnostic characteristics, clinical manifestations, and treatment strategies associated with FAS. The text of this independent study paper contains: a current literature review of FAS research history, diagnosis, clinical presentation, and implications; identification and ( screening mechanisms; and treatment strategies specific to Physical Therapists. In addition, the information contained in this independent study will be used to develop an informational booklet to be utilized by Physical Therapists and other allied health care professionals. The goal of the booklet will be to assist these professionals in the identification and treatment of children or adults with FAS