Market analysis for optoelectronic transceiver in short range data transmission

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2008.Includes bibliographical references (leaves 56-58).With the increasing demanding of bandwidth in information technology, electronic connections meet the limitation in high speed processing in shorter and shorter reach. In the work, three markets for optical connection with different reach, which range from 10km down to 1 meter, have been discussed. The 10km market denotes for the LAN standard and would mature soon. For the 100m range, active cable has emerged to meet the requirement and would penetrate the market soon. The detail analysis would be addressed on 1-10 meet market, where electronic cables have just met the limitation. Cost modeling and business plan has been conducted. After that, the conclusion and suggestions would be made on that reach.by Jia Luo.M.Eng

Simulation of interconnections in high speed integrated circuits.

The rapid development of high-speed, high-density integrated circuits has brought about a situation where the delay times and distortion of signals transmitted on the interconnections (microstrip lines) within these packages are now comparable with those of the devices in the circuit. Hence when designing high-speed digital systems the effect of signal delay, distortion, and attenuation, on these interconnections has now become a necessary part of integrated circuit design. Therefore accurate modelling and simulation of interconnects is a very important subject for research. These interconnections can create a number of problems such as signal delay, distortion, attenuation, and crosstalk between lines of close proximity. These microstrip lines have the same behaviour as exhibited by transmission lines and can therefore be described using the well-known Telegrapher's equations. A quasi-distributed equivalent circuit model describing the behaviour of such microstrip lines is implemented into the SPICE circuit simulator. This allows an investigation into lossless and lossy line characteristics and illustrates the importance of choosing the correct impedances for both the lines and devices within the integrated circuit package. The model is then extended to include crosstalk between neighbouring lines, by means of a transformation network. This study of crosstalk illustrates that logic functions lying in an intervening space between the pulse-activated lines are found to be affected more than the outside lines. The MATHEMATICA package is used for the calculation of capacitance, inductance, impedance, time delay and transformation network control parameters for any set of microstrip lines of a given geometry. The results obtained from these calculations are then used for further simulation runs using the SPICE software for different line configurations. The results obtained are seen to be consistent with all previous work conducted on coupled three line structures, and give good verification of both the Mathematica program and the SPICE equivalent circuit model

Etude de l'immunité des circuits intégrés face aux agressions électromagnétiques (proposition d'une méthode de prédiction des couplages des perturbations en mode conduit)

Avec les progrès technologiques réalisés au cours de ces dernières décennies, la complexité et les vitesses de fonctionnement des circuits intégrés ont beaucoup été augmentées. Bien que ces évolutions aient permis de diminuer les dimensions et les tensions d alimentations des circuits, la compatibilité électromagnétique (CEM) des composants a fortement été dégradée. Identifiée comme étant un verrou technologique, la CEM est aujourd hui l une des principales causes de re-design des circuits car les problématiques liées aux mécanismes de génération et de couplage du bruit ne sont pas suffisamment étudiées lors de leur conception.Ce manuscrit présente donc une méthodologie visant à étudier la propagation du bruit à travers les circuits intégrés par mesures et par simulations. Afin d améliorer nos connaissances sur la propagation d interférences électromagnétiques (IEM) et les mécanismes de couplage à travers les circuits, nous avons conçu un véhicule de test développé dans la technologie SMOS8MV® 0,25 m de Freescale Semiconductor. Dans ce circuit, plusieurs fonctions élémentaires telles qu un bus d E/S et des blocs numériques ont été implémentées. Des capteurs de tensions asynchrones ont également été intégrés sur différentes alimentations de la puce pour analyser la propagation des perturbations injectées sur les broches du composant (injection DPI) et sur les conducteurs permettant d alimenter ce dernier (injection BCI). En outre, nous proposons différents outils pour faciliter la modélisation et les simulations d immunité des circuits intégrés (extraction des modèles de PCB, approches de modélisation des systèmes d injection, méthode innovante permettant de prédire et de corréler les niveaux de tension/ de puissance injectés lors de mesures d immunité conduite, flot de modélisation). Chaque outil et méthode de modélisation proposés sont évalués sur différents cas test. Enfin, pour évaluer notre démarche de modélisation, nous l appliquons sur un bloc numérique de notre véhicule de test et comparons les résultats de simulations aux différentes mesures internes et externes réalisées sur le circuitWith technological advances in recent decades, the complexity and operating speeds of integrated circuits have greatly increased. While these developments have reduced dimensions and supply voltages of circuits, electromagnetic compatibility (EMC) of components has been highly degraded. Identified as a technological lock, EMC is now one of the main causes of circuits re-designs because issues related to generating and coupling noise mechanisms are not sufficiently studied during their design. This manuscript introduces a methodology to study propagation of electromagnetic disturbances through integrated circuits by measurements and simulations. To improve our knowledge about propagation of electromagnetic interferences (EMI) and coupling mechanisms through integrated circuits, we designed a test vehicle developed in the SMOS8MV® 0.25 m technology from Freescale Semiconductor. In this circuit, several basic functions such as I/O bus and digital blocks have been implemented. Asynchronous on-chip voltage sensors have also been integrated on different supplies of the chip to analyze propagation of disturbances injected on supply pins and wires of the component (DPI and BCI injection). In addition, we propose various tools to facilitate modeling and simulations of Integrated Circuit s immunity (PCB model extraction, injection systems modeling approaches, innovative method to predict and correlate levels of voltage / power injected during conducted immunity measurements, modeling flow). Each tool and modeling method proposed is evaluated on different test cases. To assess our modeling approach, we finally apply it on a digital block of our test vehicle and compare simulation results to various internal and external measurements performed on the circuitTOULOUSE-INSA-Bib. electronique (315559905) / SudocSudocFranceF