Tile-based Pattern Design with Topology Control

International audiencePatterns with desired aesthetic appearances and physical structures are ubiquitous.However, such patterns are challenging to produce - manual authoring requires significant expertise and efforts while automatic computation lacks sufficient flexibility and user control.We propose a method that automatically synthesizes vector patterns with visual appearance and topological structures designated by users via input exemplars and output conditions.The input can be an existing vector graphics design or a new one manually drawn by the user through our interactive interface.Our system decomposes the input pattern into constituent components (tiles) and overall arrangement (tiling).The tile sets are general and flexible enough to represent a variety of patterns, and can produce different outputs with user specified conditions such as size, shape, and topological properties for physical manufacturing

Fast, Accurate and Detailed NoC Simulations

Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router's RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a speed-up of 80-300, without compromising the cycle and bit level accuracy