Using Multi-Threshold Threshold Gates in RTD-based Logic Design. A Case Study

The basic building blocks for Resonant Tunnelling Diode (RTD) logic circuits are Threshold Gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, threshold gates can be implemented as efficiently as conventional ones, but realize more complex functions. Recently, RTD structures implementing Multi-Threshold Threshold Gates (MTTGs) have been proposed which further increase the functionality of the original TGs while maintaining their operating principle and allowing also the implementation of nanopipelining at the gate level. This paper describes the design of n-bit adders using these MTTGs. A comparison with a design based on TGs is carried out showing advantages in terms of latency, device counts and power consumption.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

Implementation and Applications of a Ternary Threshold Logic Gate

Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a designer. Most of the times, the designer sacrifices power consumption and chip area to improve delay for a given technology node. To overcome this problem, we propose a ternary threshold logic gate. We implement the proposed gate by combining threshold logic and ternary logic. Then, we construct basic building blocks of a ternary ALU (as logic gates, comparator, and arithmetic circuits) using the proposed gate. We show that the proposed ternary TLG improves delay, power consumption, and chip area of ternary circuits via simulations. Thus, the proposed gate can be used to improve delay, power consumption, and chip area of ternary circuits

Programmable neural logic

Circuits of threshold elements (Boolean input, Boolean output neurons) have been shown to be surprisingly powerful. Useful functions such as XOR, ADD and MULTIPLY can be implemented by such circuits more efficiently than by traditional AND/OR circuits. In view of that, we have designed and built a programmable threshold element. The weights are stored on polysilicon floating gates, providing long-term retention without refresh. The weight value is increased using tunneling and decreased via hot electron injection. A weight is stored on a single transistor allowing the development of dense arrays of threshold elements. A 16-input programmable neuron was fabricated in the standard 2 μm double-poly, analog process available from MOSIS. We also designed and fabricated the multiple threshold element introduced in [5]. It presents the advantage of reducing the area of the layout from O(n^2) to O(n); (n being the number of variables) for a broad class of Boolean functions, in particular symmetric Boolean functions such as PARITY. A long term goal of this research is to incorporate programmable single/multiple threshold elements, as building blocks in field programmable gate arrays

Analog circuits using FinFETs: benefits in speed-accuracy-power trade-off and simulation of parasitic effects

Multi-gate FET, e.g. FinFET devices are the most promising contenders to replace bulk FETs in sub-45 nm CMOS technologies due to their improved sub threshold and short channel behavior, associated with low leakage currents. The introduction of novel gate stack materials (e.g. metal gate, high-k dielectric) and modified device architectures (e.g. fully depleted, undoped fins) affect the analog device properties significantly. First measurements indicate enhanced intrinsic gain (<i>g<sub>m</sub>/g<sub>DS</sub></i>) and promising matching behavior of FinFETs. The resulting benefits regarding the speed-accuracy-power trade-off in analog circuit design will be shown in this work. Additionally novel device specific effects will be discussed. The hysteresis effect caused by charge trapping in high-k dielectrics or self-heating due to the high thermal resistor of the BOX isolation are possible challenges for analog design in these emerging technologies. To gain an early assessment of the impact of such parasitic effects SPICE based models are derived and applied in analog building blocks

Resource costs for fault-tolerant linear optical quantum computing

Linear optical quantum computing (LOQC) seems attractively simple: information is borne entirely by light and processed by components such as beam splitters, phase shifters and detectors. However this very simplicity leads to limitations, such as the lack of deterministic entangling operations, which are compensated for by using substantial hardware overheads. Here we quantify the resource costs for full scale LOQC by proposing a specific protocol based on the surface code. With the caveat that our protocol can be further optimised, we report that the required number of physical components is at least five orders of magnitude greater than in comparable matter-based systems. Moreover the resource requirements grow higher if the per-component photon loss rate is worse than one in a thousand, or the per-component noise rate is worse than $10^{-5}$. We identify the performance of switches in the network as the single most influential factor influencing resource scaling

Percolation, renormalization, and quantum computing with non-deterministic gates

We apply a notion of static renormalization to the preparation of entangled states for quantum computing, exploiting ideas from percolation theory. Such a strategy yields a novel way to cope with the randomness of non-deterministic quantum gates. This is most relevant in the context of optical architectures, where probabilistic gates are common, and cold atoms in optical lattices, where hole defects occur. We demonstrate how to efficiently construct cluster states without the need for rerouting, thereby avoiding a massive amount of conditional dynamics; we furthermore show that except for a single layer of gates during the preparation, all subsequent operations can be shifted to the final adapted single qubit measurements. Remarkably, cluster state preparation is achieved using essentially the same scaling in resources as if deterministic gates were available.Comment: 5 pages, 4 figures, discussion of strategies to deal with further imperfections extended, references update