Optimal microscale water cooled heat sinks for targeted alleviation of hotspot in microprocessors

This paper was presented at the 4th Micro and Nano Flows Conference (MNF2014), which was held at University College, London, UK. The conference was organised by Brunel University and supported by the Italian Union of Thermofluiddynamics, IPEM, the Process Intensification Network, the Institution of Mechanical Engineers, the Heat Transfer Society, HEXAG - the Heat Exchange Action Group, and the Energy Institute, ASME Press, LCN London Centre for Nanotechnology, UCL University College London, UCL Engineering, the International NanoScience Community, www.nanopaprika.eu.Hotspots in microprocessors arise due to non-uniform utilization of the underlying integrated circuits during chip operation. Conventional liquid cooling using microchannels leads to undercooling of the hotspot areas and overcooling of the background area of the chip resulting in excessive temperature gradients across the chip. These in turn adversely affect the chip performance and reliability. This problem becomes even more acute in multi-core processors where most of the processing power is concentrated in specific regions of the chip called as cores. We present a 1-dimensional model for quick design of a microchannel heat sink for targeted, single-phase liquid cooling of hotspots in microprocessors. The method utilizes simplifying assumptions and analytical equations to arrive at the first estimate of a microchannel heat sink design that distributes the cooling capacity of the heat sink by adapting the coolant flow and microchannel size distributions to the microprocessor power map. This distributed cooling in turn minimizes the chip temperature gradient. The method is formulated to generate a heat sink design for an arbitrary chip power map and hence can be readily utilized for different chip architectures. It involves optimization of microchannel widths for various zones of the chip power map under the operational constraints of maximum pressure drop limit for the heat sink. Additionally, it ensures that the coolant flows uninterrupted through its entire travel length consisting of microchannels of varying widths. The resulting first design estimate significantly reduces the computational effort involved in any subsequent CFD analysis required to fine tune the design for more complex flow situations arising, for example, in manifold microchannel heat sinks

System-Level Thermal-Aware Design of 3D Multiprocessors with Inter-Tier Liquid Cooling

Rising chip temperatures and aggravated thermal reliability issues have characterized the emergence of 3D multiprocessor system-on-chips (3D-MPSoCs), necessitating the development of advanced cooling technologies. Microchannel based inter-tier liquid cooling of ICs has been envisaged as the most promising solution to this problem. A system-level thermal-aware design of electronic systems becomes imperative with the advent of these new cooling technologies, in order to preserve the reliable functioning of these ICs and effective management of the rising energy budgets of high-performance computing systems. This paper reviews the recent advances in the area of systemlevel thermal modeling and management techniques for 3D multiprocessors with advanced liquid cooling. These concepts are combined to present a vision of a green data center of the future which reduces the CO2 emissions by reusing the heat it generates

Towards on-chip time-resolved thermal mapping with micro-/nanosensor arrays

In recent years, thin-film thermocouple (TFTC) array emerged as a versatile candidate in micro-/nanoscale local temperature sensing for its high resolution, passive working mode, and easy fabrication. However, some key issues need to be taken into consideration before real instrumentation and industrial applications of TFTC array. In this work, we will demonstrate that TFTC array can be highly scalable from micrometers to nanometers and that there are potential applications of TFTC array in integrated circuits, including time-resolvable two-dimensional thermal mapping and tracing the heat source of a device. Some potential problems and relevant solutions from a view of industrial applications will be discussed in terms of material selection, multiplexer reading, pattern designing, and cold-junction compensation. We show that the TFTC array is a powerful tool for research fields such as chip thermal management, lab-on-a-chip, and other novel electrical, optical, or thermal devices

CCD thermoreflectance thermography system : methodology and experimental validation

This work introduces a thermoreflectance-based system designed to measure the surface temperature field of activated microelectronic devices at submicron spatial resolution with either a laser or a CCD camera. The article describes the system, outlines the measurement methodology, and presents validation results. The thermo-reflectance thermography (TRTG) system is capable of acquiring device surface temperature fields at up to 512\u81 512 points with 0.2 ƒÊm resolution. The setup and measurement methodology are presented, along with details of the calibration process required to convert changes in measured surface reflectivity to absolute temperatures. To demonstrate the system\u81fs capabilities, standard gold micro-resistors are activated and their surface temperature fields are measured. The results of the CCD camera and our existing laser-based measurement approaches are compared and found to be in very good agreement. Finally, the system is validated by comparing the temperatures obtained with the TRTG method with those obtained from electrical resistance measurements

A new tightly-coupled transient electro-thermal simulation method for power electronics

Paper no. 224This paper presents a new transient electro-thermal (ET) simulation method for fast 3D chip-level analysis of power electronics with field solver accuracy. The metallization stacks are meshed and solved with 3D field solver using nonlinear temperature-dependent parameters, and the active devices are modeled with nonlinear tabular compact models to avoid time-consuming TCAD simulation. The main contributions include: 1) A tightly-coupled formulation that solves the electrical and thermal responses simultaneously for better convergence property; 2) Explicit account of capacitive effects, including interconnect parasitic capacitance and gate capacitance of power devices, to improve modeling accuracy in highfrequency applications; 3) A specialized transient solver based on the matrix exponential method (MEXP) to address the multi-scale problem caused by the considerably different time scales in electrical and thermal dynamics. Numerical experiments have demonstrated the advantages of the proposed co-simulation framework.postprin