Towards Practical Oblivious RAM

We take an important step forward in making Oblivious RAM (O-RAM) practical. We propose an O-RAM construction achieving an amortized overhead of 20X-35X (for an O-RAM roughly 1 terabyte in size), about 63 times faster than the best existing scheme. On the theoretic front, we propose a fundamentally novel technique for constructing Oblivious RAMs: specifically, we partition a bigger O-RAM into smaller O-RAMs, and employ a background eviction technique to obliviously evict blocks from the client-side cache into a randomly assigned server-side partition. This novel technique is the key to achieving the gains in practical performance

InSiDDe: A server for designing artificial disordered proteins

InSiDDe (In Silico Disorder Design) is a program for the in silico design of intrinsically disordered proteins of desired length and disorder probability. The latter is assessed using IUPred and spans values ranging from 0.55 to 0.95 with 0.05 increments. One to ten artificial sequences per query, each made of 50 to 200 residues, can be generated by InSiDDe. We describe the rationale used to set up InSiDDe and show that an artificial sequence of 100 residues with an IUPred score of 0.6 designed by InSiDDe could be recombinantly expressed in E. coli at high levels without degradation when fused to a natural molecular recognition element (MoRE). In addition, the artificial fusion protein exhibited the expected behavior in terms of binding modulation of the specific partner recognized by the MoRE. To the best of our knowledge, InSiDDe is the first publicly available software for the design of intrinsically disordered protein (IDP) sequences. InSiDDE is publicly available online

Performance Evaluation and Modeling of HPC I/O on Non-Volatile Memory

HPC applications pose high demands on I/O performance and storage capability. The emerging non-volatile memory (NVM) techniques offer low-latency, high bandwidth, and persistence for HPC applications. However, the existing I/O stack are designed and optimized based on an assumption of disk-based storage. To effectively use NVM, we must re-examine the existing high performance computing (HPC) I/O sub-system to properly integrate NVM into it. Using NVM as a fast storage, the previous assumption on the inferior performance of storage (e.g., hard drive) is not valid any more. The performance problem caused by slow storage may be mitigated; the existing mechanisms to narrow the performance gap between storage and CPU may be unnecessary and result in large overhead. Thus fully understanding the impact of introducing NVM into the HPC software stack demands a thorough performance study. In this paper, we analyze and model the performance of I/O intensive HPC applications with NVM as a block device. We study the performance from three perspectives: (1) the impact of NVM on the performance of traditional page cache; (2) a performance comparison between MPI individual I/O and POSIX I/O; and (3) the impact of NVM on the performance of collective I/O. We reveal the diminishing effects of page cache, minor performance difference between MPI individual I/O and POSIX I/O, and performance disadvantage of collective I/O on NVM due to unnecessary data shuffling. We also model the performance of MPI collective I/O and study the complex interaction between data shuffling, storage performance, and I/O access patterns.Comment: 10 page