A Unified Component Modeling Approach for Performance Estimation in Hardware/Software Codesign

This paper presents an approach for abstract modeling of hardware/software architectures using Hierarchical Colored Petri Nets. The approach is able to capture complex behavioral characteristics often seen in software and hardware architectures, thus it is suitable for high level codesign issues such as performance estimation. In this paper, the development of a model of the ARM7 processor [5] is described to illustrate the full potential of the modeling approach. To further illustrate the approach, a cache model is also described. The approach and related tools are currently being implemented in the LYCOS system [12]. Details and the basic characteristics of the approach can be found in [8]

An object-based codesign methodology.

The research into Codesign of Hardware and Software stems from the development of embedded systems, on which various systems restrictions are imposed. Typical restrictions can be the overall time (latency) to complete an assigned function and the space/power limits within the system. Although software can be used to undertake most tasks in an embedded system, ASIC (Application Specific Integrated Circuits) hardware components sometimes have to be recruited to meet the system constraints. Designing the restricted embedded system with both software and hardware components in it involves the analysis of not only individual hardware/software components but also their mutual influences. Using co-design principles, the approach is to consider both hardware and software from a coherent viewpoint.This thesis presents the results from our research project in the area of Codesign of Hardware and Software. In this project, we investigated previously published codesign approaches and their methodological supports. The investigation has identified shortcomings and problems with the existing codesign methodologies. A new object-based codesign approach (Co-PARSE) is thus developed in this project, which is supported by successive phases, guidelines, and techniques. This methodology offers a coherent design framework for real-time embedded systems and incorporates the criteria of system performance and hardware cost. Tools have been developed to facilitate the use of the methodology. Within the methodology, a high-level system modeling and specification approach has been developed and formalised in the Co-BSL (Codesign Behavior Specification Language). The means of transforming Co-BSL specifications to C and VHDL implementations is defined, and a library of VHDL components provided. The thesis documents the partitioning approach taken within the methodology and proposes a new multi-layered bus architecture as a basis for more flexible and efficient implementations. A means of simulating the performance characteristics of this architecture under different configurations is provided, and examples of simulation results are presented. A new embedded system (the Radio Data Computing System) is designed and simulated in the Co-PARSE methodology and simulation results analysed. The thesis concludes with an evaluation of the work carried out in the project and proposals for extending the results obtained in future research.The major contributions reported in this thesis can be summarised as follows. First, the unified system specification means has been designed, which is embodied in the Co-BSL. It captures overall dynamic aspects and performance constraints in the system under development. This high-level specification language is independent of implementation and does not bias the designer towards the use of hardware or software components at this early stage. Second, within Co-PARSE, the target architecture of the system under development has been exploited to improve the system performance and at the same time to reduce hardware cost. This novel concept has been realised by the introduction of an asynchronous bus protocol and the multi-layer bus communication structure. Third, in order to evaluate the strength and practicability of the Co-PARSE methodology, an extensive case study has been carried out. The new RDC (Radio Dada Computing) System has been designed in the proposed codesign approach. Codesign phases are subsequently applied and the guidelines and tools that are specially developed in support of the methodology are fully utilized

Timing verification in transaction modeling

Les systèmes Matériels/Logiciels deviennent indispensables dans tous les aspects de la vie quotidienne. La présence croissante de ces systèmes dans les différents produits et services incite à trouver des méthodes pour les développer efficacement. Mais une conception efficace de ces systèmes est limitée par plusieurs facteurs, certains d'entre eux sont: la complexité croissante des applications, une augmentation de la densité d'intégration, la nature hétérogène des produits et services, la diminution de temps d’accès au marché. Une modélisation transactionnelle (TLM) est considérée comme un paradigme prometteur permettant de gérer la complexité de conception et fournissant des moyens d’exploration et de validation d'alternatives de conception à des niveaux d’abstraction élevés. Cette recherche propose une méthodologie d’expression de temps dans TLM basée sur une analyse de contraintes temporelles. Nous proposons d'utiliser une combinaison de deux paradigmes de développement pour accélérer la conception: le TLM d'une part et une méthodologie d’expression de temps entre différentes transactions d’autre part. Cette synergie nous permet de combiner dans un seul environnement des méthodes de simulation performantes et des méthodes analytiques formelles. Nous avons proposé un nouvel algorithme de vérification temporelle basé sur la procédure de linéarisation des contraintes de type min/max et une technique d'optimisation afin d'améliorer l'efficacité de l'algorithme. Nous avons complété la description mathématique de tous les types de contraintes présentées dans la littérature. Nous avons développé des méthodes d'exploration et raffinement de système de communication qui nous a permis d'utiliser les algorithmes de vérification temporelle à différents niveaux TLM. Comme il existe plusieurs définitions du TLM, dans le cadre de notre recherche, nous avons défini une méthodologie de spécification et simulation pour des systèmes Matériel/Logiciel basée sur le paradigme de TLM. Dans cette méthodologie plusieurs concepts de modélisation peuvent être considérés séparément. Basée sur l'utilisation des technologies modernes de génie logiciel telles que XML, XSLT, XSD, la programmation orientée objet et plusieurs autres fournies par l’environnement .Net, la méthodologie proposée présente une approche qui rend possible une réutilisation des modèles intermédiaires afin de faire face à la contrainte de temps d’accès au marché. Elle fournit une approche générale dans la modélisation du système qui sépare les différents aspects de conception tels que des modèles de calculs utilisés pour décrire le système à des niveaux d’abstraction multiples. En conséquence, dans le modèle du système nous pouvons clairement identifier la fonctionnalité du système sans les détails reliés aux plateformes de développement et ceci mènera à améliorer la "portabilité" du modèle d'application.Hardware/Software (Hw/Sw) systems are likely to become essential in all aspects of everyday life. The increasing penetration of Hw/Sw systems in products and services creates a necessity of their efficient development. However, the productive design of these systems is limited by several factors, some of them being the increasing complexity of applications, the increasing degree of integration, the heterogeneous nature of products and services as well as the shrinking of the time-to-market delay. Transaction Level Modeling (TLM) paradigm is considered as one of the most promising simulation paradigms to break down the design complexity by allowing the exploration and validation of design alternatives at high levels of abstraction. This research proposes a timing expression methodology in TLM based on temporal constraints analysis. We propose to use a combination of two paradigms to accelerate the design process: TLM on one hand and a methodology to express timing between different transactions on the other hand. Using a timing specification model and underlining timing constraints verification algorithms can decrease the time needed for verification by simulation. Combining in one framework the simulation and analytical design exploration methods can improve the analytical power of design verification and validation. We have proposed a new timing verification algorithm based on the linearization procedure and an optimization technique to improve its efficiency. We have completed the mathematical representation of all constraint types discussed in the literature creating in this way a unified timing specification methodology that can be used in the expression of a wider class of applications than previously presented ones. We have developed the methods for communication structure exploration and refinement that permitted us to apply the timing verification algorithms in system exploration at different TLM levels. As there are many definitions of TLM and many development environments proposing TLM in their design cycle with several pro and contra, in the context of our research we define a hardware/software (Hw/Sw) specification and simulation methodology which supports TLM in such a way that several modeling concepts can be seen separately. Relying on the use of modern software engineering technologies such as XML, XSLT, XSD, object oriented programming and others supported by the .Net Framework, an approach that makes an intermediate design model reuse possible in order to cope with time-to-market constraint is presented. The proposed TLM design methodology provides a general approach in system modeling that separates various application modeling aspects from system specification: computational models, used in application modeling, supported by the language used for the functional specification and provided by simulator. As a result, in the system model we can clearly identify system functionality without details related to the development platform thereby leading to a better “portability” of the application model

Kommunikation und Bildverarbeitung in der Automation

In diesem Open-Access-Tagungsband sind die besten Beiträge des 9. Jahreskolloquiums "Kommunikation in der Automation" (KommA 2018) und des 6. Jahreskolloquiums "Bildverarbeitung in der Automation" (BVAu 2018) enthalten. Die Kolloquien fanden am 20. und 21. November 2018 in der SmartFactoryOWL, einer gemeinsamen Einrichtung des Fraunhofer IOSB-INA und der Technischen Hochschule Ostwestfalen-Lippe statt. Die vorgestellten neuesten Forschungsergebnisse auf den Gebieten der industriellen Kommunikationstechnik und Bildverarbeitung erweitern den aktuellen Stand der Forschung und Technik. Die in den Beiträgen enthaltenen anschaulichen Beispiele aus dem Bereich der Automation setzen die Ergebnisse in den direkten Anwendungsbezug

The Role of Vhdl Within the Tosca Hardware - Software Codesign Framework

This paper presents an overview of a hardware/software codesign methodology and its supporting framework (TOSCA) with emphasis on the role played by the VHDL language. The proposed approach is tailored for control-oriented applications and aims at capturing the entire codesign flow, including system cospecification, high-level partitioning, hw/sw tradeoffs, cosynthesis and cosimulation. VHDL acts as the cornerstone in the task of evaluating the outputs of the codesign flow as well as linking them to commercial simulation and synthesis environments. In particular, the paper will address the issue of simulating hardware/software architectures, focusing on the application of VHDL to the definition of an easily retargetable CPU core model by exploiting the concept of virtual kernel and customizable input/output management scheme