Channel Characterization for Chip-scale Wireless Communications within Computing Packages

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018); Torino, Italy; October 201

Epsilon-Near-Zero Grids for On-chip Quantum Networks

Realization of an on-chip quantum network is a major goal in the field of integrated quantum photonics. A typical network scalable on-chip demands optical integration of single photon sources, optical circuitry and detectors for routing and processing of quantum information. Current solutions either notoriously experience considerable decoherence or suffer from extended footprint dimensions limiting their on-chip scaling. Here we propose and numerically demonstrate a robust on-chip quantum network based on an epsilon-near-zero (ENZ) material, whose dielectric function has the real part close to zero. We show that ENZ materials strongly protect quantum information against decoherence and losses during its propagation in the dense network. As an example, we model a feasible implementation of an ENZ network and demonstrate that quantum information can be reliably sent across a titanium nitride grid with a coherence length of 434 nm, operating at room temperature, which is more than 40 times larger than state-of-the-art plasmonic analogs. Our results facilitate practical realization of large multi-node quantum photonic networks and circuits on-a-chip.Comment: 13 pages, 5 figure

An all-glass microfluidic network with integrated amorphous silicon photosensors for on-chip monitoring of enzymatic biochemical assay

A lab-on-chip system, integrating an all-glass microfluidics and on-chip optical detection, was developed and tested. The microfluidic network is etched in a glass substrate, which is then sealed with a glass cover by direct bonding. Thin film amorphous silicon photosensors have been fabricated on the sealed microfluidic substrate preventing the contamination of the micro-channels. The microfluidic network is then made accessible by opening inlets and outlets just prior to the use, ensuring the sterility of the device. The entire fabrication process relies on conventional photolithographic microfabrication techniques and is suitable for low-cost mass production of the device. The lab-on-chip system has been tested by implementing a chemiluminescent biochemical reaction. The inner channel walls of the microfluidic network are chemically functionalized with a layer of polymer brushes and horseradish peroxidase is immobilized into the coated channel. The results demonstrate the successful on-chip detection of hydrogen peroxide down to 18 mu M by using luminol and 4-iodophenol as enhancer agent

An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip

Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile System-on-Chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the communication network we analyze three wireless applications. Based on their communication requirements we observe that revisiting of the circuit switching techniques is beneficial. In this paper we propose a new energy-efficient reconfigurable circuit-switched Network-on-Chip. By physically separating the concurrent data streams we reduce the overall energy consumption. The circuit-switched router has been synthesized and analyzed for its power consumption in 0.13 ¿m technology. A 5-port circuit-switched router has an area of 0.05 mm2 and runs at 1075 MHz. The proposed architecture consumes 3.5 times less energy compared to its packet-switched equivalen