Ultra-thin plasma nitrided oxide gate dielectrics for advanced MOS transistors

Ultra-thin plasma nitrided oxides have been optimized with the objective to decrease JG and maximize carrier mobility. It was found that while the base oxide cannot be aggressively scaled, plasma optimization yields better mobility thereby increase transistor performance. A summary of the EOT versus gate leakage current density of NMOS devices with plasma nitrided oxides is shown in Figure 5.19. EOT down to 1.2 nm has been achieved with a gate leakage current density of 40 A/cm2 at 1 V operating voltage

Diffusive Transport in Quasi-2D and Quasi-1D Electron Systems

Quantum-confined semiconductor structures are the cornerstone of modern-day electronics. Spatial confinement in these structures leads to formation of discrete low-dimensional subbands. At room temperature, carriers transfer among different states due to efficient scattering with phonons, charged impurities, surface roughness and other electrons, so transport is scattering-limited (diffusive) and well described by the Boltzmann transport equation. In this review, we present the theoretical framework used for the description and simulation of diffusive electron transport in quasi-two-dimensional and quasi-one-dimensional semiconductor structures. Transport in silicon MOSFETs and nanowires is presented in detail.Comment: Review article, to appear in Journal of Computational and Theoretical Nanoscienc

Hybrid-gate deep depletion mosfet high-k zro2/diamond-based power devices

The improvement of power electronic devices, making them durable and reliable in high power environments is the key to the efficient low-carbon electrical energy production and distribution for our future energy system, eliminating the auxiliary systems and reducing the losses. Despite silicon is a well-established material it presents narrow and inadequate electrical characteristics to be use in power electronics. More efficient green electronic systems will be reached by wide band gap or ultra wide band gap semiconductors since they can provide larger blocking capabilities, higher performance-cost ratios and they can reduce the thermal requirements. Among the candidates, diamond is found to be the ultimate material to meet the power electronic trade-off between the on-resistance and the blocking capabilities. The ultra wide bandgap (UWBG) of 5.5 eV leads to a non linear increase of the performance. The higher critical electric field (> 10 MV.cm−1 ) allows the use of higher doping concentrations comparing with Si-technology. Which in combination with a superior bulk carrier mobility at room temperature for both electrons and holes (1060 cm2 .V−1 s −1 and 2100 cm2 .V−1 s −1 , respectively) favours the reduction of the devices’ resistance. Moreover, the resistivity will be reduced with increasing temperature due to the deep dopants in diamond (ionization energies of B, P or N of 0.38 eV, 0.58 eV and 1.7 eV, respectively), which result in incomplete ionization at room temperature. Likewise, the outstanding thermal conductivity (2200 W.m−1K −1 ) and the low concentration of intrinsic carriers (it is required a larger thermal energy to promote electrons from the valence band to the conduction band than in semiconductors with smaller bandgap) make diamond the most suitable material for high temperature operation. The most widely used device whether in analog or digital circuits in the Electronic Industry is the metal-oxide-semiconductor field effect transistor (MOSFET). The focus will therefore be on this type of device, particularly based on diamond, which is also the subject of this thesis. However, the upgrade to the new generation of diamond-based power MOSFETs is limited. The main issues are caused by the lack of a native oxide that meets the demanding requirements of the diamond interface. This latter degrades the performance of the devices and leads to a premature breakdown. And also by the difficulty of growing quality n-type diamond layers and the lack of efficient p-channel devices comparable to their n-channel counterparts reached by other WBGSs. It is still challenging provide devices that exploit the diamond’s properties to their full potential. This thesis proposes an alternative high-κ ZrO2/diamond-based hybrid-gate p-channel MOSFET taking advantage of the outstanding properties of these materials. In addition to the superior properties of diamond, mentioned above, zirconium dioxide contributes a barrier for holes of 2 eV, a critical electric field of 2 MV.cm−1 , a high-enthalpy of formation and an excellent thermodynamic and thermal stability. An attempt has been made to correlate the electrical behaviour of the MOS structure with the microstructural analysis. This has required an in-depth characterization that can be divided Resumen de la tesis vi in two main blocks: • Materials characterization by the use of microscopy techniques such as high resolution transmission electron microscopy (HREM), energy dispersive X-ray spectroscopy (EDX) and valence electron energy loss spectroscopy (VEELS). • Fabrication and electrical characterization of the electronic devices through different growth techniques (for both diamond and oxide thin films) such as microwave plasma assisted chemical vapour deposition (MPACVD), physical vapour deposition (PVD) and atomic layer deposition (ALD); laser lithography, metals deposition using electron beam (ebeam) evaporation and various surface and thermal treatments to finally perform the electrical measurements. In summary, this manuscript consists of the following chapters: • Chapter 1 will introduce the fabrication process methodology and state of the art of the diamond-based MOSFETs. • Chapter 2 is dedicated to the full analysis of the MOS capacitors, specially focus on understanding the behaviour of ZrO2 thin films. • Chapter 3 will deal with the implementation and characterization of this MOS structure in a novel hybrid-gate p-channel D3MOSFET. • The Overall conclusion and further outlook chapter will summarize the current status and will provide future prospective for such electronic devices.La mejora de los dispositivos electrónicos de potencia, haciéndolos duraderos y fiables en entornos de alta potencia, es la clave de la producción y distribución eficientes de los sistemas de energía eléctrica con bajas emisiones de carbono para nuestro futuro sistema energético, eliminando los sistemas auxiliares y reduciendo pérdidas. A pesar de que el silicio es un material bien establecido, presenta limitadas e inadecuadas características eléctricas para su uso en electrónica de potencia. Los sistemas ecológicos más eficientes se conseguirán a través de semiconductores de banda ancha o de banda ultra ancha, ya que pueden proporcionar una mayor capacidad de soportar alto voltaje, una mejor relación rendimiento-coste y pueden reducir los requisitos térmicos. Entre los candidatos a sustituir el Si, el diamante es el material óptimo para satisfacer el compromiso entre la resistencia de encendido y la capacidad de soportar altos voltajes que establece la electrónica de potencia. El ultra ancho de banda prohibida de 5.5 eV, conduce a un incremento no lineal del rendimiento. El mayor campo eléctrico crítico (> 10 MV.cm−1 ) permite el uso de mayores concentraciones de dopado comparado con la tecnología de Si. Lo cuál, en combinación con una movilidad de portadores en volumen a temperatura ambiente superior (1060 cm2 .V−1 s −1 y 2100 cm2 .V−1 s −1 , respectivamente) favorece la reducción de la resistencia de los dispositivos. Además, la resistividad será también reducida al incrementarse la temperatura debido a los dopantes profundos que presenta el diamante (con energías de ionización del B, P o N de 0.38 eV, 0.58 eV y 1.7 eV, respectivamente) dando lugar a una ionización incompleta a temperatura ambiente. Así mismo, la extraordinaria conductividad térmica (2200 W.m−1K −1 ) y la baja concentración de portadores intrínsecos (se necesita una energía térmica mayor para promocionar electrones desde la banda de valencia a la banda de conducción que en semiconductores con menor ancho de band prohibida) hacen del diamante el material más adecuado para operar a altas temperaturas. El dispositivo más utilizado en circuitos analógicos o digitales de la industria electrónica es el transistor de efecto de campo metal-óxido-semiconductor (MOSFET). De hecho, la mayoría de los microprocesadores comerciales se basan en este tipo de transistores. Por tanto, nos centraremos en este tipo de dispositivos, sobre todo los basados en diamante, los cuáles son objeto de esta tesis. Sin embargo, la mejora de la nueva generación de MOSFET de potencia basados en diamante es limitada. Los principales problemas se deben a la falta de un óxido nativo que cumpla los exigentes requisitos de la interfaz de diamante. Esto último degrada el rendimiento de los dispositivos y conduce a una avería prematura. Y también por la dificultad de crecer capas de diamante de tipo n de calidad y la falta de dispositivos eficientes de canal p comparables a sus homólogos de canal n alcanzados por otros WBGS. Sigue siendo un reto proporcionar dispositivos que exploten al máximo las propiedades del diamante. En esta tesis se propone un transistor de efecto campo metal-óxido-semiconductor (MOSFET en sus siglas en inglés) de canal p y puerta híbrida basado en diamante y en un óxido de alta constante dieléctrica, ZrO2, aprovechando las excelentes propiedades de estos materiales. En combinación con las extraordinarias propiedades del diamante, mencionadas anteriormente, el dióxido de zirconio contribuye con una barrera para huecos de 2 eV, un campo eléctrico crítico de 2 MV.cm−1 , una alta entalpía de formación y una excelente estabilidad térmica y termodinámica. Se ha intentado correlacionar el comportamiento eléctrico de la estructura MOS con el análisis microestructural. Esto ha requerido de una caracterización en profundidad que se puede dividir en dos grandes bloques: • Caracterización de materiales mediante el uso de técnicas de microscopía como microscopía electrónica de transmisión de alta resolución (HREM, en sus siglas en inglés), espectroscopía de rayos X de energía dispersiva (EDX, en sus siglas en inglés) y espectroscopía de pérdida de energía de electrones de valencia (VEELS, en sus siglas en inglés). • Fabricación y caracterización eléctrica de los dispositivos electrónicos mediante diferentes técnicas de crecimiento (tanto para capas de diamante como películas finas de óxido) tales como deposición química en fase vapor asistida por plasma de microondas (MPACVD, en sus siglas en inglés), deposición física en fase vapor (PVD, en sus siglas en inglés) y deposición en capa atómica (ALD, en sus siglas en inglés); litografía láser, deposición de metales mediante evaporación por haz de electrones (ebeam, en sus siglas en inglés) y diversos tratamientos superficiales y térmicos para finalmente realizar las medidas eléctricas. En resumen, esta tesis consta de los siguientes capítulos: • El capítulo 1 presenta la metodología del proceso de fabricación y el estado del arte de los MOSFETs basados en diamante. • El capítulo 2 está dedicado al análisis completo de los condensadores MOS, se centra especialmente en la comprensión del comportamiento de las películas delgadas de ZrO2. • El capítulo 3 tratará sobre la implementación y caracterización de esta estructura MOS en un novedoso MOSFET en modo depleción profunda de canal p de compuerta híbrida. • En el capítulo Conclusiones generales y perspectivas de futuro, se resumirá el estado actual y se expondrán las perspectivas futuras de este tipo de dispositivos electrónicos.136 página

Physical and Electronic Properties of Nanoscale 2D Materials

There is a great push towards reducing the size scale of both electronic components and machines. Two dimensional materials, such as graphene, are ideal candidates towards this push, as they are naturally atomically thin. In the case of nanoscale machines, the mechanical properties of the material surfaces become increasingly important. The use of laminar materials, such as graphene and MoS2, to modify the surface properties, yet maintain nanoscale topographical features, are very attractive. Towards this goal, we have investigated the surface properties of MoS2 at the nanoscale using Lateral Force Microscopy (LFM). In these investigations, we measure periodic frictional features with periodicity of ~ 4 nm. Ultrashort devices that incorporate atomically thin components have the potential to be the smallest electronics. Such extremely scaled devices are expected to show ballistic nonlinear behavior that could make them tremendously useful for ultra fast electronic applications. We report nonlinear electron transport in ultrashort channel graphene devices. We observe this nonlinear response up to room temperature, with zero applied magnetic field, on a readily accessible oxide substrate. This makes the nanogap technology we utilize of great potential for achieving extremely scaled high-speed atomically thin devices

PHONON-ENERGY-COUPLING-ENHANCEMENT EFFECT AND ITS APPLICATIONS

Silicon Oxide/Oxynitride (SiO2/SiON) has been the mainstream material used for gate dielectric for MOS transistors for the past 30 years. The aggressive scaling of the feature size of MOS transistor has limited the ability of SiO2/SiON to work effectively as the gate dielectric to modulate the conduction of current of MOS transistors due to excess leakage current dominated by direct quantum tunneling. Due to this constraint, alternative gate dielectric/high-k is being employed to reduce the leakage current in order to maintain the rate of scaling of MOS transistors. However, the cost involved in the implementation of these new gate dielectric materials are high due to the requirements of a change in the process flow for device fabrication. This work presents the results of a novel processing method implementing the use of rapid thermal processing (RTP) on conventional SiO2/SiON gate dielectric to reduce the gate leakage current by three to five orders of magnitude. Electrical properties of the effect were characterized on fabricated MOS capacitors using semiconductor parameter analyzer and LCR meter. Material characterization was performed using FT-IR to understand the mechanism involved in this novel processing method, named PECE (Phonon-Energy-Coupling-Enhancement). By implementing this novel process, the use of SiO2/SiON as gate dielectric can be scaled further in conventional process flow of device fabrication

Tuning ultrafast electron thermalization pathways in a van der Waals heterostructure

Ultrafast electron thermalization - the process leading to Auger recombination, carrier multiplication via impact ionization and hot carrier luminescence - occurs when optically excited electrons in a material undergo rapid electron-electron scattering to redistribute excess energy and reach electronic thermal equilibrium. Due to extremely short time and length scales, the measurement and manipulation of electron thermalization in nanoscale devices remains challenging even with the most advanced ultrafast laser techniques. Here, we overcome this challenge by leveraging the atomic thinness of two-dimensional van der Waals (vdW) materials in order to introduce a highly tunable electron transfer pathway that directly competes with electron thermalization. We realize this scheme in a graphene-boron nitride-graphene (G-BN-G) vdW heterostructure, through which optically excited carriers are transported from one graphene layer to the other. By applying an interlayer bias voltage or varying the excitation photon energy, interlayer carrier transport can be controlled to occur faster or slower than the intralayer scattering events, thus effectively tuning the electron thermalization pathways in graphene. Our findings, which demonstrate a novel means to probe and directly modulate electron energy transport in nanoscale materials, represent an important step toward designing and implementing novel optoelectronic and energy-harvesting devices with tailored microscopic properties.Comment: Accepted to Nature Physic

An Investigation of Carrier Transport in Hafnium Oxide/Silicon Dioxide MOS Gate Dielectric Stacks from 5.6-400K

Hafnium oxide (HfO2) is replacing silicon dioxide (SiO2) as the gate dielectric in metal oxide semiconductor (MOS) structures driven mainly by need to reduce high leakage currents observed in sub-2nm SiO2. The high dielectric constant of HfO2 (~25) compared to SiO2 (3.9 bulk) allows a thicker HfO2 layer to be used in place of the thinner SiO2 layer thereby reducing the gate leakage current in MOS devices while maintaining the same capacitive coupling provided by the thinner SiO2. However, incorporating HfO2 into MOS devices produces a SiO2 interfacial layer between the Si substrate and HfO2 interface. The increased complexity of the multilayer dielectric gate stack and introduction of new materials requires knowledge of the carrier transport mechanisms for accurate modeling and process improvement. A large temperature dependence of the leakage current in HfO2 gate dielectrics are observed compared to SiO2, indicating temperature dependent leakage current measurements maybe well suited to understand the transport mechanism of HfO2-based gate dielectrics. The leakage currents are measured for two different titanium nitride (TiN) metal gate stacks composed of either 3nm or 5nm HfO2 on 1.1nm SiO2 interfacial layer over temperatures ranging from 6K to 400K. For gate biases that yield equivalent electron energy barriers for the 3nm and 5nm HfO2gate stacks, the 5nm stack shows orders of magnitude less current and an order of magnitude larger increase in the gate leakage current with respect to temperature from 5.6K to 400K. Knowledge of the energy band structure is crucial in determining what carrier transport mechanisms are plausible in multilayer dielectric stacks. Important parameters, necessary for modeling different transport mechanisms, can be extracted from accurately constructed energy band diagrams such as electric fields and barrier heights. An existing program developed by the author is further modified to incorporate image charge effects, multilayer dielectrics, and transmission coefficient calculations for use in this study. Results indicate that the widely used Poole-Frenkel and Schottky conduction mechanisms for HfO2 dielectrics can only explain a narrow electric field and temperature range and fail to explain the observed thickness dependence. Modeling the temperature dependence of 3nm and 5nm HfO2/1.1nm SiO2 n/pMOSFETs with a combination of a temperature independent term, variable range hopping conduction, and Arrhenius expression (e.g., nearest neighbor hopping) describes the entire measured temperature range (6K to 400K). Additionally, HfO2 defect densities can be extracted using the proposed model and provide densities in the range of ~1019 to ~1021 cm-3 eV-1, which correlate well with defect densities reported in the literature. Defects in the HfO2 are likely a result of oxygen vacancies