5,286 research outputs found

    Undergraduate Catalog of Studies, 2023-2024

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    Undergraduate Catalog of Studies, 2023-2024

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    Wide-band spectrum sensing with convolution neural network using spectral correlation function

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    Recognition of signals is a spectrum sensing challenge requiring simultaneous detection, temporal and spectral localization, and classification. In this approach, we present the convolution neural network (CNN) architecture, a powerful portrayal of the cyclo-stationarity trademark, for remote range detection and sign acknowledgment. Spectral correlation function is used along with CNN. In two scenarios, method-1 and method-2, the suggested approach is used to categorize wireless signals without any previous knowledge. Signals are detected and classified simultaneously in method-1. In method-2, the sensing and classification procedures take place sequentially. In contrast to conventional spectrum sensing techniques, the proposed CNN technique need not bother with a factual judgment process or past information on the signs’ separating qualities. The method beats both conventional sensing methods and signal-classifying deep learning networks when used to analyze real-world, over-the-air data in cellular bands. Despite the implementation’s emphasis on cellular signals, any signal having cyclo-stationary properties may be detected and classified using the provided approach. The proposed model has achieved more than 90% of testing accuracy at 15 dB

    A database accelerator for energy-efficient query processing and optimization

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    Data processing on a continuously growing amount of information and the increasing power restrictions have become an ubiquitous challenge in our world today. Besides parallel computing, a promising approach to improve the energy efficiency of current systems is to integrate specialized hardware. This paper presents a Tensilica RISC processor extended with an instruction set to accelerate basic database operators frequently used in modern database systems. The core was taped out in a 28 nm SLP CMOS technology and allows energy-efficient query processing as well as query optimization by applying selectivity estimation techniques. Our chip measurements show an 1000x energy improvement on selected database operators compared to state-of-the-art systems

    LIPIcs, Volume 251, ITCS 2023, Complete Volume

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    LIPIcs, Volume 251, ITCS 2023, Complete Volum

    Blind Concealment from Reconstruction-based Attack Detectors for Industrial Control Systems via Backdoor Attacks

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    Industrial Control Systems (ICS) are responsible for the safety and operations of critical infrastructure such as power grids. Attacks on such systems threaten the well-being of societies, and the lives of human operators, and pose huge financial risks. Due to their reliance on insecure legacy protocols and hosts, the systems cannot be protected easily. Fortunately, detailed process data is available and can be leveraged by process-aware attack detectors that verify inherent physical correlations. In commercial products, such detectors will be trained by the vendors on process data from the target system, which might allow malicious manipulations of the training process to later evade detection at runtime. Previously proposed attacks in this direction rely on detailed process knowledge to predict the exact attack features to be concealed. In this work, we show that even without any process knowledge, it is possible to launch training time attacks against such attack detectors. Our backdoor attacks achieve this by identifying `alien' actuator state combinations that never occur in the training samples and injecting them with legitimate sensor data into the training set. At runtime, the attacker spoofs one of those alien actuator state combinations, which triggers (regardless of current process sensor values) the classification as `normal'. To demonstrate this, we design and implement five backdoor attacks against autoencoder-based anomaly detectors for 14 attacks from the BATADAL dataset collection. Out of these five variations, four implementations have been found to be effective. Our evaluation also shows that our best backdoor attack implementation can achieve perfect attack concealment and accomplish an average accuracy of 0.19. Compared to the performance of the detector for anomalies that are not concealed by inserted triggers, our attacks decrease the detector's accuracy by 0.39

    Consensus Algorithms of Distributed Ledger Technology -- A Comprehensive Analysis

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    The most essential component of every Distributed Ledger Technology (DLT) is the Consensus Algorithm (CA), which enables users to reach a consensus in a decentralized and distributed manner. Numerous CA exist, but their viability for particular applications varies, making their trade-offs a crucial factor to consider when implementing DLT in a specific field. This article provided a comprehensive analysis of the various consensus algorithms used in distributed ledger technologies (DLT) and blockchain networks. We cover an extensive array of thirty consensus algorithms. Eleven attributes including hardware requirements, pre-trust level, tolerance level, and more, were used to generate a series of comparison tables evaluating these consensus algorithms. In addition, we discuss DLT classifications, the categories of certain consensus algorithms, and provide examples of authentication-focused and data-storage-focused DLTs. In addition, we analyze the pros and cons of particular consensus algorithms, such as Nominated Proof of Stake (NPoS), Bonded Proof of Stake (BPoS), and Avalanche. In conclusion, we discuss the applicability of these consensus algorithms to various Cyber Physical System (CPS) use cases, including supply chain management, intelligent transportation systems, and smart healthcare.Comment: 50 pages, 20 figure

    Undergraduate Catalog of Studies, 2022-2023

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    ACiS: smart switches with application-level acceleration

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    Network performance has contributed fundamentally to the growth of supercomputing over the past decades. In parallel, High Performance Computing (HPC) peak performance has depended, first, on ever faster/denser CPUs, and then, just on increasing density alone. As operating frequency, and now feature size, have levelled off, two new approaches are becoming central to achieving higher net performance: configurability and integration. Configurability enables hardware to map to the application, as well as vice versa. Integration enables system components that have generally been single function-e.g., a network to transport data—to have additional functionality, e.g., also to operate on that data. More generally, integration enables compute-everywhere: not just in CPU and accelerator, but also in network and, more specifically, the communication switches. In this thesis, we propose four novel methods of enhancing HPC performance through Advanced Computing in the Switch (ACiS). More specifically, we propose various flexible and application-aware accelerators that can be embedded into or attached to existing communication switches to improve the performance and scalability of HPC and Machine Learning (ML) applications. We follow a modular design discipline through introducing composable plugins to successively add ACiS capabilities. In the first work, we propose an inline accelerator to communication switches for user-definable collective operations. MPI collective operations can often be performance killers in HPC applications; we seek to solve this bottleneck by offloading them to reconfigurable hardware within the switch itself. We also introduce a novel mechanism that enables the hardware to support MPI communicators of arbitrary shape and that is scalable to very large systems. In the second work, we propose a look-aside accelerator for communication switches that is capable of processing packets at line-rate. Functions requiring loops and states are addressed in this method. The proposed in-switch accelerator is based on a RISC-V compatible Coarse Grained Reconfigurable Arrays (CGRAs). To facilitate usability, we have developed a framework to compile user-provided C/C++ codes to appropriate back-end instructions for configuring the accelerator. In the third work, we extend ACiS to support fused collectives and the combining of collectives with map operations. We observe that there is an opportunity of fusing communication (collectives) with computation. Since the computation can vary for different applications, ACiS support should be programmable in this method. In the fourth work, we propose that switches with ACiS support can control and manage the execution of applications, i.e., that the switch be an active device with decision-making capabilities. Switches have a central view of the network; they can collect telemetry information and monitor application behavior and then use this information for control, decision-making, and coordination of nodes. We evaluate the feasibility of ACiS through extensive RTL-based simulation as well as deployment in an open-access cloud infrastructure. Using this simulation framework, when considering a Graph Convolutional Network (GCN) application as a case study, a speedup of on average 3.4x across five real-world datasets is achieved on 24 nodes compared to a CPU cluster without ACiS capabilities

    Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead

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    As time-critical systems require timing guarantees, Worst-Case Execution Times (WCET) have to be employed. However, WCET estimation methods usually assume fault-free hardware. If proper actions are not taken, such fault-free WCET approaches become unsafe, when faults impact the hardware during execution. The majority of approaches, dealing with hardware faults, address the impact of faults on the functional behavior of an application, i.e., denial of service and binary correctness. Few approaches address the impact of faults on the application timing behavior, i.e., time to finish the application, and target faults occurring in memories. However, as the transistor size in modern technologies is significantly reduced, faults in cores cannot be considered negligible anymore. This work shows that faults not only affect the functional behavior, but they can have a significant impact on the timing behavior of applications. To expose the overall impact of faults, we enhance vulnerability analysis to include not only functional, but also timing correctness, and show that faults impact WCET estimations. As common techniques to deal with faults, such as watchdog timers and re-execution, have large timing overhead for error detection and correction, we propose a mechanism with near-zero and bounded timing overhead. A RISC-V core is used as a case study. The obtained results show that faults can lead up to almost 700% increase in the maximum observed execution time between fault-free and faulty execution without protection, affecting the WCET estimations. On the contrary, the proposed mechanism is able to restore fault-free WCET estimations with a bounded overhead of 2 execution cycles
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