Doctor of Philosophy

dissertationWireless communications pervade all avenues of modern life. The rapid expansion of wireless services has increased the need for transmission schemes that are more spectrally efficient. Dynamic spectrum access (DSA) systems attempt to address this need by building a network where the spectrum is used opportunistically by all users based on local and regional measurements of its availability. One of the principal requirements in DSA systems is to initialize and maintain a control channel to link the nodes together. This should be done even before a complete spectral usage map is available. Additionally, with more users accessing the spectrum, it is important to maintain a stable link in the presence of significant interference in emergency first-responders, rescue, and defense applications. In this thesis, a new multicarrier spread spectrum (MC-SS) technique based on filter banks is presented. The new technique is called filter bank multicarrier spread spectrum (FB-MC-SS). A detailed theory of the underlying properties of this signal are given, with emphasis on the properties that lend themselves to synchronization at the receiver. Proposed algorithms for synchronization, channel estimation, and detection are implemented on a software-defined radio platform to complete an FB-MC-SS transceiver and to prove the practicality of the technique. FB-MC-SS is shown through physical experimentation to be significantly more robust to partial band interference compared to direct sequence spread spectrum. With a higher power interfering signal occupying 90% of its band, FB-MC-SS maintains a low bit error rate. Under the same interference conditions, DS-SS fails completely. This experimentation leads to a theoretical analysis that shows in a frequency selective channel with additive white noise, the FB-MC-SS system has performance that equals that obtained by a DS-SS system employing an optimal rake receiver. This thesis contains a detailed chapter on implementation and design, including lessons learned while prototyping the system. This is to assist future system designers to quickly gain proficiency in further development of this technology

Chip and Signature Interleaving in DS CDMA Systems

Siirretty Doriast

On biunimodular vectors for unitary matrices

A biunimodular vector of a unitary matrix $A \in U(n)$ is a vector v \in \mathbb{T}^n\subset\bc^n such that $Av \in \mathbb{T}^n$ as well. Over the last 30 years, the sets of biunimodular vectors for Fourier matrices have been the object of extensive research in various areas of mathematics and applied sciences. Here, we broaden this basic harmonic analysis perspective and extend the search for biunimodular vectors to arbitrary unitary matrices. This search can be motivated in various ways. The main motivation is provided by the fact, that the existence of biunimodular vectors for an arbitrary unitary matrix allows for a natural understanding of the structure of all unitary matrices

Graph Signal Processing: Overview, Challenges and Applications

Research in Graph Signal Processing (GSP) aims to develop tools for processing data defined on irregular graph domains. In this paper we first provide an overview of core ideas in GSP and their connection to conventional digital signal processing. We then summarize recent developments in developing basic GSP tools, including methods for sampling, filtering or graph learning. Next, we review progress in several application areas using GSP, including processing and analysis of sensor network data, biological data, and applications to image processing and machine learning. We finish by providing a brief historical perspective to highlight how concepts recently developed in GSP build on top of prior research in other areas.Comment: To appear, Proceedings of the IEE

Toatie : functional hardware description with dependent types

Describing correct circuits remains a tall order, despite four decades of evolution in Hardware Description Languages (HDLs). Many enticing circuit architectures require recursive structures or complex compile-time computation — two patterns that prove difficult to capture in traditional HDLs. In a signal processing context, the Fast FIR Algorithm (FFA) structure for efficient parallel filtering proves to be naturally recursive, and most Multiple Constant Multiplication (MCM) blocks decompose multiplications into graphs of simple shifts and adds using demanding compile time computation. Generalised versions of both remain mostly in academic folklore. The implementations which do exist are often ad hoc circuit generators, written in software languages. These pose challenges for verification and are resistant to composition. Embedded functional HDLs, that represent circuits as data, allow for these descriptions at the cost of forcing the designer to work at the gate-level. A promising alternative is to use a stand-alone compiler, representing circuits as plain functions, exemplified by the CλaSH HDL. This, however, raises new challenges in capturing a circuit’s staging — which expressions in the single language should be reduced during compile-time elaboration, and which should remain in the circuit’s run-time? To better reflect the physical separation between circuit phases, this work proposes a new functional HDL (representing circuits as functions) with first-class staging constructs. Orthogonal to this, there are also long-standing challenges in the verification of parameterised circuit families. Industry surveys have consistently reported that only a slim minority of FPGA projects reach production without non-trivial bugs. While a healthy growth in the adoption of automatic formal methods is also reported, the majority of testing remains dynamic — presenting difficulties for testing entire circuit families at once. This research offers an alternative verification methodology via the combination of dependent types and automatic synthesis of user-defined data types. Given precise enough types for synthesisable data, this environment can be used to develop circuit families with full functional verification in a correct-by-construction fashion. This approach allows for verification of entire circuit families (not just one concrete member) and side-steps the state-space explosion of model checking methods. Beyond the existing work, this research offers synthesis of combinatorial circuits — not just a software model of their behaviour. This additional step requires careful consideration of staging, erasure & irrelevance, deriving bit representations of user-defined data types, and a new synthesis scheme. This thesis contributes steps towards HDLs with sufficient expressivity for awkward, combinatorial signal processing structures, allowing for a correct-by-construction approach, and a prototype compiler for netlist synthesis.Describing correct circuits remains a tall order, despite four decades of evolution in Hardware Description Languages (HDLs). Many enticing circuit architectures require recursive structures or complex compile-time computation — two patterns that prove difficult to capture in traditional HDLs. In a signal processing context, the Fast FIR Algorithm (FFA) structure for efficient parallel filtering proves to be naturally recursive, and most Multiple Constant Multiplication (MCM) blocks decompose multiplications into graphs of simple shifts and adds using demanding compile time computation. Generalised versions of both remain mostly in academic folklore. The implementations which do exist are often ad hoc circuit generators, written in software languages. These pose challenges for verification and are resistant to composition. Embedded functional HDLs, that represent circuits as data, allow for these descriptions at the cost of forcing the designer to work at the gate-level. A promising alternative is to use a stand-alone compiler, representing circuits as plain functions, exemplified by the CλaSH HDL. This, however, raises new challenges in capturing a circuit’s staging — which expressions in the single language should be reduced during compile-time elaboration, and which should remain in the circuit’s run-time? To better reflect the physical separation between circuit phases, this work proposes a new functional HDL (representing circuits as functions) with first-class staging constructs. Orthogonal to this, there are also long-standing challenges in the verification of parameterised circuit families. Industry surveys have consistently reported that only a slim minority of FPGA projects reach production without non-trivial bugs. While a healthy growth in the adoption of automatic formal methods is also reported, the majority of testing remains dynamic — presenting difficulties for testing entire circuit families at once. This research offers an alternative verification methodology via the combination of dependent types and automatic synthesis of user-defined data types. Given precise enough types for synthesisable data, this environment can be used to develop circuit families with full functional verification in a correct-by-construction fashion. This approach allows for verification of entire circuit families (not just one concrete member) and side-steps the state-space explosion of model checking methods. Beyond the existing work, this research offers synthesis of combinatorial circuits — not just a software model of their behaviour. This additional step requires careful consideration of staging, erasure & irrelevance, deriving bit representations of user-defined data types, and a new synthesis scheme. This thesis contributes steps towards HDLs with sufficient expressivity for awkward, combinatorial signal processing structures, allowing for a correct-by-construction approach, and a prototype compiler for netlist synthesis

Introduction to frames

This survey gives an introduction to redundant signal representations called frames. These representations have recently emerged as yet another powerful tool in the signal processing toolbox and have become popular through use in numerous applications. Our aim is to familiarize a general audience with the area, while at the same time giving a snapshot of the current state-of-the-art