The pseudo-exhaustive test of sequential circuits

The concept of a pseudoexhaustive test for sequential circuits is introduced. Instead of test sets one applies pseudoexhaustive test sequences of a limited length, which provides well-known benefits as far as fault coverage, self-test capability, and simplicity of test generation are concerned. Some flip flops and latches are integrated into an incomplete scan path, such that each possible state of the circuit is reachable within a few steps. Some more flip flops and some new segmentation cells are added to the partial scan path in order to make a pseudoexhaustive test feasible. Algorithms for placing these devices automatically are presented. Also it is shown how to transform a pseudoexhaustive test set into a pseudoexhaustive test sequence of a similar size. The analyzed examples show that a conventional complete scan path without additional testability features requires more hardware overhead than the proposed test strategy, which retains all the known benefits of a pseudoexhaustive test

Testing a Quantum Computer

The problem of quantum test is formally addressed. The presented method attempts the quantum role of classical test generation and test set reduction methods known from standard binary and analog circuits. QuFault, the authors software package generates test plans for arbitrary quantum circuits using the very efficient simulator QuIDDPro[1]. The quantum fault table is introduced and mathematically formalized, and the test generation method explained.Comment: 15 pages, 17 equations, 27 tables, 8 figure

Testing a Quantum Computer

We address the problem of quantum test set generation using measurement from a single basis and the single fault model. Experimental physicists currently test quantum circuits exhaustively, meaning that each n-bit permutative circuit requires ζ x 2n tests to assure functionality, and for an m stage permutative circuit proven not to function properly the current method requires ζ x 2n x m tests as the upper bound for fault localization, where zeta varies with physical implementation. Indeed, the exhaustive methods complexity grows exponentially with the number of qubits, proportionally to the number of stages in a quantum circuit and directly with zeta. This testability bound grows still exponentially with the attempted verification of quantum effects, such as the emission of a quantum source. The exhaustive method will soon not be feasible for practical application provided the number of qubits increases even a small number from the current state of the art. An algorithm is presented making fault detection feasible both now and in the foreseeable future for quantum circuits. The presented method attempts the quantum role of classical test generation and test set reduction methods known from standard binary and analog circuits. The quantum fault table is introduced, and the test generation method explained, we show that all faults can be detected that impact calculations from the computational basis. It is believed that this fundamental research will lead to the simplification of testing for commercial quantum computers

The Pseudo-Exhaustive Test of Sequential Circuits

The concept of a pseudoexhaustive test for sequen-tial circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the pre-sented test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation