A Review of Cooling and Lubrication Techniques for ‎Machining Difficult-to-cut Material

Superalloys have magnificent properties which make them widely applied in various industrial fields. They possess high mechanical properties such as high strength, high rupture resistance, and high resistance to corrosion and oxidation. Since they can maintain these properties even at elevated temperatures, they face some problems during the cutting and machining process. They are classified as difficult-to-cut alloys, which means that high heat is generated in the cutting zone due to their poor thermal conductivity. In addition, high friction takes place between the tool and the chip. To overcome these problems during their machining process, different cooling and lubrication techniques via suitable cutting fluids are highly recommended. In this study, we review the cooling and lubrication techniques that have been applied by authors in machining superalloys such as dry machining, flood cooling, high-pressure jet machining, minimum quantity lubrication and cooling, and cryogenic machining. The technique of each type followed by its advantages and disadvantages are mentioned

DESIGN OF EFFICIENT NANOELECTRONIC MEMORY AND CRYPTOGRAPHIC CIRCUITS

This thesis presents the design of Nanoelectronic Memory cell and arrays compatible with molecular switch (nanodevice) electrical characteristics. The proposed transmission gate based CMOL (hybrid CMOS / Molecular) memory cell surmounts the operational difficulties facing previous design. The Control circuitry with improved multiplexer design is introduced in this dissertation. Yield improvement through replacing the defective cell with a free cell can be achieved using a proposed algorithm. Moreover, the proposed memory cell has the same area as the existing CMOL inverter cells allowing easier implementation of both logic and memory circuits on the same chip. An efficient hardware implementation of the SBox from the Advanced Encryption Standard (AES) is presented in this dissertation. Modification of the design was achieved by adding Tri­ state Inverter followed by an Inverter (TII). Simulation results show a reduction in the average power dissipation as well as the time delays. Reduction of supply voltage and using low Vdd in non critical path improved the performance by reducing the energy delay product. Different transistors models with dual threshold voltage (Vt) based on 65nm CMOS technology were applied to the design to achieve further improvement. Keywords: CMOL, CMOL circuits, Nanoscale memory, Control Circuit, AES, SBox, Deep sub-micron CMOS technology, Tri-state Inverter, Low Power SBo