A simulation and architectural study of TCP/IP

This paper discusses current network technologies and protocols and presents a simulation study of the most common networking protocol used today, TCP/IP. The TCP/IP protocol stack has many inherent problems that will be shown through this simulation study. Using the SimpleScalar Toolset, the significance of the data copying and checksumming performed in TCP/IP will be shown along with the architecture needed to support the processing of TCP/IP. Solutions for these TCP/IP pitfalls including a zero-copy protocol and a design for an intelligent network interface card will also be presented

A general framework to realize an abstract machine as an ILP processor with application to java

Ph.DDOCTOR OF PHILOSOPH

Procedure graphs and computer optimizations.

by Ho Kei Shiu Edward.Thesis (M.Phil.)--Chinese University of Hong Kong, 1992.Includes bibliographical references (leaves 199-202).AcknowledgementAbstractChapter Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Initial Motivations --- p.1Chapter 1.2 --- Objectives of Our Study --- p.2Chapter 1.3 --- Outline of the Thesis --- p.3Chapter Chapter 2 --- Basics of the Procedure Graph Theory --- p.6Chapter 2.1 --- Introducing Procedure Graph Theory --- p.6Chapter 2.1.1 --- "Nodes, Arcs and Pseudo-time Labels" --- p.7Chapter 2.2 --- Examples --- p.12Chapter 2.3 --- Exploring the Meanings of the Pseudo-time Labels --- p.13Chapter 2.4 --- Equivalence and Transformation --- p.16Chapter 2.4.1 --- Equivalence --- p.16Chapter 2.4.2 --- Transmission Track and Causality Preservation --- p.16Chapter 2.4.3 --- Transformation --- p.17Chapter 2.4.3.1 --- Serial-to-Parallel Transformations (SP) --- p.18Chapter 2.4.3.2 --- Parallel-to-Serial Transformations (PS) --- p.20Chapter 2.4.3.3 --- Store-Store Cancellations (SSC) --- p.21Chapter 2.4.3.4 --- Normalization of Pseudo-time Labels --- p.23Chapter 2.4.3.5 --- Boundary Conditions and Multi-level Pseudo-time Labels --- p.24Chapter 2.5 --- Procedure Graph Optimizations --- p.28Chapter 2.5.1 --- Representing Dependencies --- p.28Chapter 2.5.2 --- Eliminating Unnecessary Dependencies --- p.32Chapter 2.6 --- Simulation Program --- p.36Chapter 2.6.1 --- Preliminary Study Using the Simulation Program --- p.36Chapter 2.6.2 --- Economic Factors --- p.37Chapter 2.6.3 --- Combinatorial Explosion of Procedure Graphs --- p.38Chapter Chapter 3 --- Extending the Procedure Graph Theory --- p.45Chapter 3.1 --- The T-Operator and the F-Operator --- p.45Chapter 3.2 --- Modifying the Firing Rule --- p.46Chapter 3.3 --- Procedure Graph Representation for Different Branch Strategies --- p.49Chapter 3.3.1 --- Multiple-Path Execution --- p.49Chapter 3.3.2 --- Conditional Execution with Delayed Commitment of Results --- p.51Chapter 3.3.3 --- Speculative Execution with Register Backup and Branch Repair --- p.52Chapter 3.4 --- Procedure Graph Representation for a Stack --- p.56Chapter 3.5 --- Vector Forwarding --- p.58Chapter 3.5.1 --- An Example of Vector Chaining in Cray-1 --- p.58Chapter 3.5.2 --- "Vector SP, PS and SSC" --- p.59Chapter 3.5.3 --- A Note Concerning the Use of Algorithmic Time Labels --- p.61Chapter 3.5.4 --- Further Consideration of Vector Forwarding --- p.62Chapter Chapter 4 --- Hardware Realization of Procedure Graph Optimizations --- p.64Chapter 4.1 --- Node-Oriented Versus Arc-Oriented Representation --- p.64Chapter 4.2 --- Backward Pointers Versus Forward Pointers --- p.65Chapter 4.3 --- Backward Pointers as Hardware Tags --- p.69Chapter 4.4 --- Pointer Algebra --- p.72Chapter 4.4.1 --- Serial-to-Parallel Transformations --- p.72Chapter 4.4.2 --- Store-Store Cancellations --- p.73Chapter 4.4.3 --- Parallel-to-Serial Transformations --- p.74Chapter 4.5 --- Drawbacks of Using Backward Pointers --- p.75Chapter 4.6 --- Multiple Tags --- p.76Chapter Chapter 5 --- A Backward-Pointer Representation Scheme :The T-Architecture --- p.82Chapter 5.1 --- The T-Architecture --- p.82Chapter 5.2 --- Local Addressing Space Within the CPU --- p.83Chapter 5.3 --- Why Reservation Stations --- p.84Chapter 5.4 --- Memory Data Forwarding --- p.89Chapter 5.4.1 --- The Updating Buffer --- p.90Chapter 5.4.2 --- Ordering and Consistency --- p.96Chapter 5.4.2.1 --- Store After Store --- p.96Chapter 5.4.2.2 --- Store After Load --- p.97Chapter 5.5 --- Speculative Execution --- p.97Chapter 5.5.1 --- Procedural Dependencies --- p.97Chapter 5.5.2 --- Branch Instruction Format --- p.98Chapter 5.5.3 --- Branch Prediction --- p.99Chapter 5.5.4 --- Branch Instruction Unit --- p.99Chapter 5.5.5 --- Register Backups --- p.100Chapter 5.5.5.1 --- Branch is Correctly Predicted --- p.101Chapter 5.5.5.2 --- Branch Repair --- p.102Chapter 5.5.5.3 --- Example --- p.102Chapter 5.5.6 --- Total Ordering Memory Stores --- p.110Chapter 5.5.7 --- Simplifying the Checkpoint Repair Mechanism --- p.112Chapter 5.6 --- A Simulator for the T-Architecture --- p.113Chapter 5.6.1 --- Basic Configuration of the Simulator --- p.114Chapter 5.6.2 --- Parameters of the Simulator --- p.115Chapter 5.6.3 --- Benchmark Programs --- p.116Chapter 5.7 --- Experiments --- p.118Chapter 5.7.1 --- Experiment1 --- p.119Chapter 5.7.2 --- Experiment2 --- p.121Chapter 5.7.3 --- Experiment3 --- p.123Chapter 5.7.4 --- Experiment4 --- p.127Chapter Chapter 6 --- Predictive Procedure Graph Optimizations in the S-Prototype --- p.137Chapter 6.1 --- Keys to Higher Performance --- p.138Chapter 6.2 --- The Superscalar Approach --- p.139Chapter 6.3 --- Processor Architecture of the S-Prototype --- p.139Chapter 6.4 --- Design Strategies of the S-Prototype --- p.141Chapter 6.4.1 --- Fetching Multiple Instructions --- p.142Chapter 6.4.2 --- Handling Procedural Dependencies : Branching Instructions --- p.142Chapter 6.4.2.1 --- Branch Unit and Branch Predicting Buffer --- p.143Chapter 6.4.2.2 --- Branch Repairing - Recovering Machine State --- p.144Chapter 6.4.3 --- Extensive Tagging and Result Forwarding --- p.147Chapter 6.4.4 --- Static and Dynamic Data Dependencies --- p.148Chapter 6.4.4.1 --- Handling Static Dependencies by using the Multitag Pool --- p.149Chapter 6.4.4.2 --- Handling Dynamic Dependencies by using the Reservation Stations --- p.150Chapter 6.4.5 --- Extracting Parallelism --- p.152Chapter 6.4.5.1 --- Representing Data Dependency in the Multitag Pool --- p.153Chapter 6.4.5.2 --- Implementing Transformation Rules --- p.156Chapter 6.4.6 --- Out-of-order Issue and Execution --- p.157Chapter 6.4.7 --- Memory Accesses --- p.158Chapter 6.4.8 --- Bus Contention and Arbitration --- p.160Chapter Chapter 7 --- An Attempt To Simulate Procedure Graphs Using Graph Grammar --- p.161Chapter 7.1 --- Introducing Graph Grammar --- p.161Chapter 7.2 --- Basic Concepts in Sequential Graph Grammar --- p.161Chapter 7.2.1 --- Production Rules and Interface Graph --- p.162Chapter 7.2.2 --- Gluing Constructions and Pushouts --- p.162Chapter 7.2.3 --- Gluing Conditions --- p.163Chapter 7.3 --- Initial Considerations to Simulate Procedure Graphs --- p.165Chapter 7.4 --- Example --- p.165Chapter 7.5 --- Problems Encountered --- p.167Chapter 7.6 --- Some Insights into the Unsolved Problem --- p.168Chapter 7.7 --- "Parallelism, Concurrency and New Transformation Rules" --- p.171Chapter Chapter 8 --- Representing Causality Using Petri Nets --- p.175Chapter 8.1 --- Defining Petri Nets --- p.175Chapter 8.1.1 --- Petri Nets as a Tool for System Modeling --- p.176Chapter 8.1.2 --- The Characteristics of a Petri Net --- p.177Chapter 8.1.3 --- Useful Extensions --- p.178Chapter 8.2 --- Program Analysis and Modeling Computer Operations --- p.179Chapter 8.2.1 --- Representing Causality Relationships --- p.180Chapter 8.2.2 --- Representing the Total Ordering of Instructions in a Sequential Program --- p.184Chapter 8.3 --- Extending the Model --- p.186Chapter 8.4 --- Comparing Procedure Graphs and Petri Nets --- p.188Chapter Chapter 9 --- Conclusion and Future Research Directions --- p.190Chapter 9.1 --- Formalizing the Procedure Graph Theory --- p.190Chapter 9.2 --- Mathematical Properties of Procedure Graphs --- p.191Chapter 9.3 --- Register Abuses --- p.192Chapter 9.4 --- Hardware Representation of Procedure Graphs --- p.194Chapter 9.5 --- Tags Describing Tags --- p.196Chapter 9.6 --- Software Optimizations --- p.197Chapter 9.7 --- Simulation Programs --- p.198References --- p.19