4 research outputs found
Test-Delivery Optimization in Manycore SOCs
We present two test-data delivery optimization algorithms
for system-on-chip (SOC) designs with hundreds of cores,
where a network-on-chip (NOC) is used as the interconnection
fabric. We first present an e ective algorithm based on a subsetsum
formulation to solve the test-delivery problem in NOCs
with arbitrary topology that use dedicated routing. We further
propose an algorithm for the important class of NOCs with grid
topology and XY routing. The proposed algorithm is the first to
co-optimize the number of access points, access-point locations,
pin distribution to access points, and assignment of cores to access
points for optimal test resource utilization of such NOCs. Testtime
minimization is modeled as an NOC partitioning problem
and solved with dynamic programming in polynomial time. Both
the proposed methods yield high-quality results and are scalable
to large SOCs with many cores. We present results on synthetic
grid topology NOC-based SOCs constructed using cores from
the ITC’02 benchmark, and demonstrate the scalability of our
approach for two SOCs of the future, one with nearly 1,000 cores
and the other with 1,600 cores. Test scheduling under power
constraints is also incorporated in the optimization framework
Studies on Core-Based Testing of System-on-Chips Using Functional Bus and Network-on-Chip Interconnects
The tests of a complex system such as a microprocessor-based system-onchip
(SoC) or a network-on-chip (NoC) are difficult and expensive. In this thesis,
we propose three core-based test methods that reuse the existing functional
interconnects-a flat bus, hierarchical buses of multiprocessor SoC's (MPSoC),
and a N oC-in order to avoid the silicon area cost of a dedicated test access mechanism
(TAM). However, the use of functional interconnects as functional TAM's
introduces several new problems.
During tests, the interconnects-including the bus arbitrator, the bus bridges,
and the NoC routers-operate in the functional mode to transport the test stimuli
and responses, while the core under tests (CUT) operate in the test mode. Second,
the test data is transported to the CUT through the functional bus, and not
directly to the test port. Therefore, special core test wrappers that can provide
the necessary control signals required by the different functional interconnect are
proposed. We developed two types of wrappers, one buffer-based wrapper for the
bus-based systems and another pair of complementary wrappers for the NoCbased
systems.
Using the core test wrappers, we propose test scheduling schemes for the three
functionally different types of interconnects. The test scheduling scheme for a flat
bus is developed based on an efficient packet scheduling scheme that minimizes
both the buffer sizes and the test time under a power constraint. The schedulingscheme is then extended to take advantage of the hierarchical bus architecture of
the MPSoC systems. The third test scheduling scheme based on the bandwidth
sharing is developed specifically for the NoC-based systems. The test scheduling
is performed under the objective of co-optimizing the wrapper area cost and the
resulting test application time using the two complementary NoC wrappers.
For each of the proposed methodology for the three types of SoC architec ..
ture, we conducted a thorough experimental evaluation in order to verify their
effectiveness compared to other methods
Integrating simultaneous bi-direction signalling in the test fabric of 3D stacked integrated circuits.
Jennions, Ian K. - Associate SupervisorThe world has seen significant advancements in electronic devices’ capabilities,
most notably the ability to embed ultra-large-scale functionalities in lightweight,
area and power-efficient devices. There has been an enormous push towards
quality and reliability in consumer electronics that have become an indispensable
part of human life. Consequently, the tests conducted on these devices at the
final stages before these are shipped out to the customers have a very high
significance in the research community. However, researchers have always
struggled to find a balance between the test time (hence the test cost) and the
test overheads; unfortunately, these two are inversely proportional.
On the other hand, the ever-increasing demand for more powerful and compact
devices is now facing a new challenge. Historically, with the advancements in
manufacturing technology, electronic devices witnessed miniaturizing at an
exponential pace, as predicted by Moore’s law. However, further geometric or
effective 2D scaling seems complicated due to performance and power concerns
with smaller technology nodes. One promising way forward is by forming 3D
Stacked Integrated Circuits (SICs), in which the individual dies are stacked
vertically and interconnected using Through Silicon Vias (TSVs) before being
packaged as a single chip. This allows more functionality to be embedded with a
reduced footprint and addresses another critical problem being observed in 2D
designs: increasingly long interconnects and latency issues. However, as more
and more functionality is embedded into a small area, it becomes increasingly
challenging to access the internal states (to observe or control) after the device
is fabricated, which is essential for testing. This access is restricted by the limited
number of Chip Terminals (IC pins and the vertical Through Silicon Vias) that a
chip could be fitted with, the power consumption concerns, and the chip area
overheads that could be allocated for testing.
This research investigates Simultaneous Bi-Directional Signaling (SBS) for use
in Test Access Mechanism (TAM) designs in 3D SICs. SBS enables chip
terminals to simultaneously send and receive test vectors on a single Chip
Terminal (CT), effectively doubling the per-pin efficiency, which could be
translated into additional test channels for test time reduction or Chip Terminal
reduction for resource efficiency. The research shows that SBS-based test
access methods have significant potential in reducing test times and/or test
resources compared to traditional approaches, thereby opening up new avenues
towards cost-effectiveness and reliability of future electronics.PhD in Manufacturin