Small-world interconnection networks for large parallel computer systems

The use of small-world graphs as interconnection networks of multicomputers is proposed and analysed in this work. Small-world interconnection networks are constructed by adding (or modifying) edges to an underlying local graph. Graphs with a rich local structure but with a large diameter are shown to be the most suitable candidates for the underlying graph. Generation models based on random and deterministic wiring processes are proposed and analysed. For the random case basic properties such as degree, diameter, average length and bisection width are analysed, and the results show that a fast transition from a large diameter to a small diameter is experienced when the number of new edges introduced is increased. Random traffic analysis on these networks is undertaken, and it is shown that although the average latency experiences a similar reduction, networks with a small number of shortcuts have a tendency to saturate as most of the traffic flows through a small number of links. An analysis of the congestion of the networks corroborates this result and provides away of estimating the minimum number of shortcuts required to avoid saturation. To overcome these problems deterministic wiring is proposed and analysed. A Linear Feedback Shift Register is used to introduce shortcuts in the LFSR graphs. A simple routing algorithm has been constructed for the LFSR and extended with a greedy local optimisation technique. It has been shown that a small search depth gives good results and is less costly to implement than a full shortest path algorithm. The Hilbert graph on the other hand provides some additional characteristics, such as support for incremental expansion, efficient layout in two dimensional space (using two layers), and a small fixed degree of four. Small-world hypergraphs have also been studied. In particular incomplete hypermeshes have been introduced and analysed and it has been shown that they outperform the complete traditional implementations under a constant pinout argument. Since it has been shown that complete hypermeshes outperform the mesh, the torus, low dimensional m-ary d-cubes (with and without bypass channels), and multi-stage interconnection networks (when realistic decision times are accounted for and with a constant pinout), it follows that incomplete hypermeshes outperform them as well

2005 Literary Review (no. 18)

https://poetcommons.whittier.edu/greenleafreview/1015/thumbnail.jp

Reports to the President

A compilation of annual reports for the 1999-2000 academic year, including a report from the President of the Massachusetts Institute of Technology, as well as reports from the academic and administrative units of the Institute. The reports outline the year's goals, accomplishments, honors and awards, and future plans

The Chordal Spoke ATM Interconnection Network

Networks of workstations have become a popular platform for parallel computing. The use of Asynchronous Transfer Mode (ATM) interconnection networks can improve the communication characteristics of these parallel clusters. This paper presents Chordal Spoke (CS) networks which are a class of topologies built from small ATM switches. These networks are cost effective and scalable to include a large number of processors. The CS network topology is presented along with an addressing scheme which provides efficient communication between processors. The low diameter and scalable bisection width of CS networks give them a performance advantage over traditional workstation cluster configurations. We show that CS networks compare favorably with other multicomputer topologies in terms of several important metrics. Index Terms: Multi-hop ATM networks, interconnection networks, switching networks, embedding, routing, fault tolerance, multicomputers. y This research was supported by Sprint Corpora..