292 research outputs found
On the accuracy and hardware requirements of cordic based phased array calibration
Abstract included in text
On the accuracy and hardware requirements of cordic based phased array calibration
Abstract included in text
Implementation of the Trigonometric LMS Algorithm using Original Cordic Rotation
The LMS algorithm is one of the most successful adaptive filtering
algorithms. It uses the instantaneous value of the square of the error signal
as an estimate of the mean-square error (MSE). The LMS algorithm changes
(adapts) the filter tap weights so that the error signal is minimized in the
mean square sense. In Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS), two
new versions of LMS algorithms, same formulations are performed as in the LMS
algorithm with the exception that filter tap weights are now expressed using
trigonometric and hyperbolic formulations, in cases for TLMS and HLMS
respectively. Hence appears the CORDIC algorithm as it can efficiently perform
trigonometric, hyperbolic, linear and logarithmic functions. While
hardware-efficient algorithms often exist, the dominance of the software
systems has kept those algorithms out of the spotlight. Among these hardware-
efficient algorithms, CORDIC is an iterative solution for trigonometric and
other transcendental functions. Former researches worked on CORDIC algorithm to
observe the convergence behavior of Trigonometric LMS (TLMS) algorithm and
obtained a satisfactory result in the context of convergence performance of
TLMS algorithm. But revious researches directly used the CORDIC block output in
their simulation ignoring the internal step-by-step rotations of the CORDIC
processor. This gives rise to a need for verification of the convergence
performance of the TLMS algorithm to investigate if it actually performs
satisfactorily if implemented with step-by-step CORDIC rotation. This research
work has done this job. It focuses on the internal operations of the CORDIC
hardware, implements the Trigonometric LMS (TLMS) and Hyperbolic LMS (HLMS)
algorithms using actual CORDIC rotations. The obtained simulation results are
highly satisfactory and also it shows that convergence behavior of HLMS is much
better than TLMS.Comment: 12 pages, 5 figures, 1 table. Published in IJCNC;
http://airccse.org/journal/cnc/0710ijcnc08.pdf,
http://airccse.org/journal/ijc2010.htm
A Sharp Double Inequality for the Inverse Tangent Function
The inverse tangent function can be bounded by different inequalities, for
example by Shafer's inequality. In this publication, we propose a new sharp
double inequality, consisting of a lower and an upper bound, for the inverse
tangent function. In particular, we sharpen Shafer's inequality and calculate
the best corresponding constants. The maximum relative errors of the obtained
bounds are approximately smaller than 0.27% and 0.23% for the lower and upper
bound, respectively. Furthermore, we determine an upper bound on the relative
errors of the proposed bounds in order to describe their tightness
analytically. Moreover, some important properties of the obtained bounds are
discussed in order to describe their behavior and achieved accuracy.Comment: Submitted to the Transactions on Information Theor
A fast CORDIC co-processor architecture for digital signal processing applications
The coordinate rotational digital computer (CORDIC) is an arithmetic algorithm, which has been used for arithmetic units in the fast computing of elementary functions and for special purpose hardware in programmable logic devices. This paper describes a classification method that can be used for the possible applications of the algorithm and the architecture that is required for fast hardware computing of the algorithm.Área: Redes - Sistemas Operativos - Sistemas de Tiempo Real - Arquitectura de Procesadore
FPGA-Based Bandwidth Selection for Kernel Density Estimation Using High Level Synthesis Approach
FPGA technology can offer significantly hi\-gher performance at much lower
power consumption than is available from CPUs and GPUs in many computational
problems. Unfortunately, programming for FPGA (using ha\-rdware description
languages, HDL) is a difficult and not-trivial task and is not intuitive for
C/C++/Java programmers. To bring the gap between programming effectiveness and
difficulty the High Level Synthesis (HLS) approach is promoting by main FPGA
vendors. Nowadays, time-intensive calculations are mainly performed on GPU/CPU
architectures, but can also be successfully performed using HLS approach. In
the paper we implement a bandwidth selection algorithm for kernel density
estimation (KDE) using HLS and show techniques which were used to optimize the
final FPGA implementation. We are also going to show that FPGA speedups,
comparing to highly optimized CPU and GPU implementations, are quite
substantial. Moreover, power consumption for FPGA devices is usually much less
than typical power consumption of the present CPUs and GPUs.Comment: 23 pages, 6 figures, extended version of initial pape
Electronics and data acquisition demonstrator for a kinetic inductance camera
A prototype of digital frequency multiplexing electronics allowing the real
time monitoring of kinetic inductance detector (KIDs) arrays for mm-wave
astronomy has been developed. It requires only 2 coaxial cables for
instrumenting a large array. For that, an excitation comb of frequencies is
generated and fed through the detector. The direct frequency synthesis and the
data acquisition relies heavily on a large FPGA using parallelized and
pipelined processing. The prototype can instrument 128 resonators (pixels) over
a bandwidth of 125 MHz. This paper describes the technical solution chosen, the
algorithm used and the results obtained
A fast CORDIC co-processor architecture for digital signal processing applications
The coordinate rotational digital computer (CORDIC) is an arithmetic algorithm, which has been used for arithmetic units in the fast computing of elementary functions and for special purpose hardware in programmable logic devices. This paper describes a classification method that can be used for the possible applications of the algorithm and the architecture that is required for fast hardware computing of the algorithm.Área: Redes - Sistemas Operativos - Sistemas de Tiempo Real - Arquitectura de ProcesadoresRed de Universidades con Carreras en Informática (RedUNCI
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