Testable synthesis of high complex control devices

High complex control devices can be described by interactive FSMs (IFSMs) which can be derived from representations based on hardware description languages (VHDL or Verilog). The description of each FSM can be modified by adding the characteristic to be, in test mode, transparent to data flow. The complete testability of the IFSM is thus achieved by connecting fully testable implementations of each modified FSM. In this way, test sequences separately generated for each FSM can be directly applied to the IFSM. The aim of this paper is to demonstrate that the addition of test functionality to each FSM description and its simultaneous synthesis with the FSM functionality, produces a lower area overhead than that necessary for the application of a partial-scan technique

Testable Synthesis of High Complex Control Devices

High complex control devices can be described by interactive FSMs (IFSMs) which can be derived from representations based on hardware description languages (VHDL or Verilog) [3]. The description of each FSM can be modified by adding the characteristic to be, in test mode, transparent to data flow. The complete testability of the IFSM is thus achieved by connecting fully testable implementations of each modified FSM. In this way, test sequences separately generated for each FSM can be directly applied to the IFSM. The aim of this paper is to demonstrate that the addition of test functionality to each FSM description, and its simultaneous synthesis with the FSM functionality, produces a lower area overhead than that necessary for the application of a partialscan technique. I. Introduction Testable synthesis is usually approached at the gate or register-transfer level. In the past years a large number of Design for Testability (DfT) techniques have been proposed [1] and the scan-path tec..