Transition-fault test generation

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.Includes bibliographical references (leaf 18).After an integrated circuit is manufactured, it must be tested to insure that it is not defective. Specifically, timing defects are becoming increasingly important to detect because of the decreasing process geometries and increasing clock rates. One way to detect these timing defects is to apply test patterns to the integrated circuit that are generated using the transition-fault model. Unfortunately, industry's current transition-fault test generation schemes produce test sets that are too large to store in the memory of the tester. The proposed methods of test generation utilize stuck-at-fault tests to create transition-fault test sets of a smaller size. Greedy algorithms are used in the generation of both the stuck-at-fault and transition-fault tests. In addition, various methods of test set compaction are explored to further reduce the size of the test sets. This research demonstrates an effective way to generate compact transition-fault test sets for a benchmark circuit and holds great promise for application to large commercial circuits

AN APPROACH TO DEVELOP INTELLIGENT DIGITAL TEST SYSTEMS

A new test generation method is developed for digital systems on the basis of alternative graphs. Tests are generated using symbolic signal values and are organized in the compact way - in form of symbolic test programs and data arrays. A new architecture is pro- posed for test systems which is suited for on-line generating deterministic test patterns in algorithmic way. Special features are implemented in test generator and tester to support event driven testing, which makes it possible to test dynamically devices that work at higher clock rates than the tester does

SoC Test: Trends and Recent Standards

The well-known approaching test cost crisis, where semiconductor test costs begin to approach or exceed manufacturing costs has led test engineers to apply new solutions to the problem of testing System-On-Chip (SoC) designs containing multiple IP (Intellectual Property) cores. While it is not yet possible to apply generic test architectures to an IP core within a SoC, the emergence of a number of similar approaches, and the release of new industry standards, such as IEEE 1500 and IEEE 1450.6, may begin to change this situation. This paper looks at these standards and at some techniques currently used by SoC test engineers. An extensive reference list is included, reflecting the purpose of this publication as a review paper

An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator

A New architecture of Built-In Self-Diagnosis is presented in this project. The logic Built-In-Self-Test architecture method is extreme response compaction architecture. This architecture first time enables an autonomous on-chip evaluation of test responses with negligible hardware overhead. Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session. Due to some reasons, the existing method Built-In Self-Test is less often applied to random logic than to embedded memories.  The generation of deterministic test patterns can become prohibitively high due to hardware overhead. The diagnostic resolution of compacted test responses is in many cases poor and the overhead required for an acceptable resolution may become too high.  Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement. The modified Built-In-Self-Test circuit incorporates a fault syndrome compression scheme and improves the circuit speed with reduction of time

Pseudofunctional Delay Tests For High Quality Small Delay Defect Testing

Testing integrated circuits to verify their operating frequency, known as delay testing, is essential to achieve acceptable product quality. The high cost of functional testing has driven the industry to automatically-generated structural tests, applied by low-cost testers taking advantage of design-for-test (DFT) circuitry on the chip. Traditional at-speed functional testing of digital circuits is increasingly challenged by new defect types and the high cost of functional test development. This research addressed the problems of accurate delay testing in DSM circuits by targeting resistive open and short circuits, while taking into account manufacturing process variation, power dissipation and power supply noise. In this work, we developed a class of structural delay tests in which we extended traditional launch-on-capture delay testing to additional launch and capture cycles. We call these Pseudofunctional Tests (PFT). A test pattern is scanned into the circuit, and then multiple functional clock cycles are applied to it with at-speed launch and capture for the last two cycles. The circuit switching activity over an extended period allows the off-chip power supply noise transient to die down prior to the at-speed launch and capture, achieving better timing correlation with the functional mode of operation. In addition, we also proposed advanced compaction methodologies to compact the generated test patterns into a smaller test set in order to reduce the test application time. We modified our CodGen K longest paths per gate automatic test pattern generator to implement PFT pattern generation. Experimental results show that PFT test generation is practical in terms of test generation time

New Techniques to Reduce the Execution Time of Functional Test Programs

The compaction of test programs for processor-based systems is of utmost practical importance: Software-Based Self-Test (SBST) is nowadays increasingly adopted, especially for in-field test of safety-critical applications, and both the size and the execution time of the test are critical parameters. However, while compacting the size of binary test sequences has been thoroughly studied over the years, the reduction of the execution time of test programs is still a rather unexplored area of research. This paper describes a family of algorithms able to automatically enhance an existing test program, reducing the time required to run it and, as a side effect, its size. The proposed solutions are based on instruction removal and restoration, which is shown to be computationally more efficient than instruction removal alone. Experimental results demonstrate the compaction capabilities, and allow analyzing computational costs and effectiveness of the different algorithms

Efficient Path Delay Test Generation with Boolean Satisfiability

This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver. Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure

Efficient Test Compaction for Combinational Circuits Based on Fault Detection Count-Directed Clustering

Test compaction is an effective technique for reducing test data volume and test application time. In this paper, we present a new static test compaction algorithm based on test vector decomposition and clustering. Test vectors are decomposed and clustered in an increasing order of faults detection count. This clustering order gives more degree of freedom and results in better compaction. Experimental results demonstrate the effectiveness of the proposed approach in achieving higher compaction in a much more efficient CPU time than previous clustering-based test compaction approaches