2 research outputs found

    Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology

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    This paper presents a new 32-bit adder structure with 12 GHz low-power operation in 65nm technology. The Fast Conditional Sparse-Tree Logic (FCSL) is based on modifying the initial Sparse-Tree architecture [1] to enhance its speed using tertiary trees and applying a carry-select scheme in some of the more significant bits. This design has been compared with the Sparse-Tree adder and the Low-Voltage Swing adder in terms of speed and power. It has been shown that speed can be improved using FCSL architecture while keeping the power at a comparable level

    Smart hardware designs for probabilistically-analyzable processor architectures

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    Future Critical Real-Time Embedded Systems (CRTES), like those is planes, cars or trains, require more and more guaranteed performance in order to satisfy the increasing performance demands of advanced complex software features. While increased performance can be achieved by deploying processor techniques currently used in High-Performance Computing (HPC) and mainstream domains, their use challenges the software timing analysis, a necessary step in CRTES' verification and validation. Cache memories are known to have high impact in performance, and in fact, current CRTES include multicores usually with several levels of cache. In this line, this Thesis aims at increasing the guaranteed performance of CRTES by using techniques for caches building upon time randomization and providing probabilistic guarantees of tasks' execution time. In this Thesis, we first focus on on improving cache placement and replacement to improve guaranteed performance. For placement, different existing policies are explored in a multi-level cache setup, and a solution is reached in which different of those policies are combined. For cache replacement, we analyze a pathological scenario that no cache policy so far accounts and propose several policies that fix this pathological scenario. For shared caches in multicore we observe that contention is mainly caused by private writes that go through to the shared cache, yet using a pure write-back policy also has its drawbacks. We propose a hybrid approach to mitigate this contention. Building on this solution, the next contribution tackles a problem caused by the need of some reliability mechanisms in CRTES. Implementing reliability close to the processor's core has a significant impact in performance. A look-ahead error detection solution is proposed to greatly mitigate the performance impact. The next contribution proposes the first hardware prefetcher for CRTES with arbitrary cache hierarchies. Given its speculative nature, prefetchers that have a guaranteed positive impact on performance are difficult to design. We present a framework that provides execution time guarantees and obtains a performance benefit. Finally, we focus on the impact of timing anomalies in CRTES with caches. For the first time, a definition and taxonomy of timing anomalies is given for Measurement-Based Timing Analysis. Then, we focus on a specific timing anomaly that can happen with caches and provide a solution to account for it in the execution time estimates.Los Sistemas Empotrados de Tiempo-Real Cr铆tico (SETRC), como los de los aviones, coches o trenes, requieren m谩s y m谩s rendimiento garantizado para satisfacer la demanda al alza de rendimiento para funciones complejas y avanzadas de software. Aunque el incremento en rendimiento puede ser adquirido utilizando t茅cnicas de arquitectura de procesadores actualmente utilizadas en la Computaci贸n de Altas Prestaciones (CAP) i en los dominios convencionales, este uso presenta retos para el an谩lisis del tiempo de software, un paso necesario en la verificaci贸n y validaci贸n de SETRC. Las memorias caches son conocidas por su gran impacto en rendimiento y, de hecho, los actuales SETRC incluyen multicores normalmente con diversos niveles de cache. En esta l铆nea, esta Tesis tiene como objetivo mejorar el rendimiento garantizado de los SETRC utilizando t茅cnicas para caches y utilizando m茅todos como la randomizaci贸n del tiempo y proveyendo garant铆as probabil铆sticas de tiempo de ejecuci贸n de las tareas. En esta Tesis, primero nos centramos en mejorar la colocaci贸n y el reemplazo de caches para mejorar el rendimiento garantizado. Para la colocaci贸n, diferentes pol铆ticas son exploradas en un sistema cache multi-nivel, y se llega a una soluci贸n donde diversas de estas pol铆ticas son combinadas. Para el reemplazo, analizamos un escenario patol贸gico que ninguna pol铆tica actual tiene en cuenta, y proponemos varias pol铆ticas que solucionan este escenario patol贸gico. Para caches compartidas en multicores, observamos que la contenci贸n es causada principalmente por escrituras privadas que van a trav茅s de la cache compartida, pero usar una pol铆tica de escritura retardada pura tambi茅n tiene sus consecuencias. Proponemos un enfoque h铆brido para mitigar la contenci贸n. Sobre esta soluci贸n, la siguiente contribuci贸n ataca un problema causado por la necesidad de mecanismos de fiabilidad en SETRC. Implementar fiabilidad cerca del n煤cleo del procesador tiene un impacto significativo en rendimiento. Una soluci贸n basada en anticipaci贸n se propone para mitigar el impacto en rendimiento. La siguiente contribuci贸n propone el primer prefetcher hardware para SETRC con una jerarqu铆a de caches arbitraria. Por primera vez, se da una definici贸n y taxonom铆a de anomal铆as temporales para An谩lisis Temporal Basado en Medidas. Despu茅s, nos centramos en una anomal铆a temporal concreta que puede pasar con caches y ofrecemos una soluci贸n que la tiene en cuenta en las estimaciones del tiempo de ejecuci贸n.Postprint (published version
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