A Techniques for Scalable and Effective Routability Evaluation

Routing congestion has become a critical layout challenge in nanoscale circuits since it is a critical factor in determining the routability of a design. An unroutable design is not useful even though it closes on all other design metrics. Fast design closure can only be achieved by accurately evaluating whether a design is routable or not early in the design cycle. Lately, it has become common to use a “light mode ” version of a global router to quickly evaluate the routability of a given placement. This approach suffers from three weaknesses: (i) it does not adequately model local routing resources, which can cause incorrect routability predictions that are only detected late, during detailed routing, (ii) the congestion maps obtained by it tend to have isolated hot spots surrounded by noncongested spots, called “noisy hot spots”, which further affects the accuracy in routability evaluation, (iii) the metrics used to represent congestion may yield numbers that do not provide sufficient intuition to the designer; moreover, they may often fail to predict the routability accurately. This paper presents solutions to these issues. First, we propose three approaches to model local routing resources. Second, we propose a smoothing technique to reduce the number of noisy hot spots and obtain a more accurate routability evaluation result. Finally, we develop a new metric which represents congestion maps with higher fidelity. We apply the proposed techniques to several industrial circuits and demonstrate that one can better predict and evaluate design routability, and congestion mitigation tools can perform muc

Virtual and topological coordinate based routing, mobility tracking and prediction in 2D and 3D wireless sensor networks

2013 Fall.Includes bibliographical references.A Virtual Coordinate System (VCS) for Wireless Sensor Networks (WSNs) characterizes each sensor node's location using the minimum number of hops to a specific set of sensor nodes called anchors. VCS does not require geographic localization hardware such as Global Positioning System (GPS), or localization algorithms based on Received Signal Strength Indication (RSSI) measurements. Topological Coordinates (TCs) are derived from Virtual Coordinates (VCs) of networks using Singular Value Decomposition (SVD). Topology Preserving Maps (TPMs) based on TCs contain 2D or 3D network topology and directional information that are lost in VCs. This thesis extends the scope of VC and TC based techniques to 3D sensor networks and networks with mobile nodes. Specifically, we apply existing Extreme Node Search (ENS) for anchor placement for 3D WSNs. 3D Geo-Logical Routing (3D-GLR), a routing algorithm for 3D sensor networks that alternates between VC and TC domains is evaluated. VC and TC based methods have hitherto been used only in static networks. We develop methods to use VCs in mobile networks, including the generation of coordinates, for mobile sensors without having to regenerate VCs every time the topology changes. 2D and 3D Topological Coordinate based Tracking and Prediction (2D-TCTP and 3D-TCTP) are novel algorithms developed for mobility tracking and prediction in sensor networks without the need of physical distance measurements. Most existing 2D sensor networking algorithms fail or perform poorly in 3D networks. Developing VC and TC based algorithms for 3D sensor networks is crucial to benefit from the scalability, adjustability and flexibility of VCs as well as to overcome the many disadvantages associated with geographic coordinate systems. Existing ENS algorithm for 2D sensor networks plays a key role in providing a good anchor placement and we continue to use ENS algorithm for anchor selection in 3D network. Additionally, we propose a comparison algorithm for ENS algorithm named Double-ENS algorithm which uses two independent pairs of initial anchors and thereby increases the coverage of ENS anchors in 3D networks, in order to further prove if anchor selection from original ENS algorithm is already optimal. Existing Geo-Logical Routing (GLR) algorithm demonstrates very good routing performance by switching between greedy forwarding in virtual and topological domains in 2D sensor networks. Proposed 3D-GLR extends the algorithm to 3D networks by replacing 2D TCs with 3D TCs in TC distance calculation. Simulation results show that the 3D-GLR algorithm with ENS anchor placement can significantly outperform current Geographic Coordinates (GCs) based 3D Greedy Distributed Spanning Tree Routing (3D-GDSTR) algorithm in various network environments. This demonstrates the effectiveness of ENS algorithm and 3D-GLR algorithm in 3D sensor networks. Tracking and communicating with mobile sensors has so far required the use of localization or geographic information. This thesis presents a novel approach to achieve tracking and communication without geographic information, thus significantly reducing the hardware cost and energy consumption. Mobility of sensors in WSNs is considered under two scenarios: dynamic deployment and continuous movement. An efficient VC generation scheme, which uses the average of neighboring sensors' VCs, is proposed for newly deployed sensors to get coordinates without flooding based VC generation. For the second scenario, a prediction and tracking algorithm called 2D-TCTP for continuously moving sensors is developed for 2D sensor networks. Predicted location of a mobile sensor at a future time is calculated based on current sampled velocity and direction in topological domain. The set of sensors inside an ellipse-shaped detection area around the predicted future location is alerted for the arrival of mobile sensor for communication or detection purposes. Using TPMs as a 2D guide map, tracking and prediction performances can be achieved similar to those based on GCs. A simple modification for TPMs generation is proposed, which considers radial information contained in the first principle component from SVD. This modification improves the compression or folding at the edges that has been observed in TPMs, and thus the accuracy of tracking. 3D-TCTP uses a detection area in the shape of a 3D sphere. 3D-TCTP simulation results are similar to 2D-TCTP and show competence comparable to the same algorithms based on GCs although without any 3D geographic information

Skybridge-3D-CMOS: A Fine-Grained Vertical 3D-CMOS Technology Paving New Direction for 3D IC

2D CMOS integrated circuit (IC) technology scaling faces severe challenges that result from device scaling limitations, interconnect bottleneck that dominates power and performance, etc. 3D ICs with die-die and layer-layer stacking using Through Silicon Vias (TSVs) and Monolithic Inter-layer Vias (MIVs) have been explored in recent years to generate circuits with considerable interconnect saving for continuing technology scaling. However, these 3D IC technologies still rely on conventional 2D CMOS’s device, circuit and interconnect mindset showing only incremental benefits while adding new challenges reliability issues, robustness of power delivery network design and short-channel effects as technology node scaling. Skybridge-3D-CMOS (S3DC) is a fine-grained 3D IC fabric that uses vertically-stacked gates and 3D interconnections composed on vertical nanowires to yield orders of magnitude benefits over 2D ICs. This 3D fabric fully uses the vertical dimension instead of relying on a multi-layered 2D mindset. Its core fabric aspects including device, circuit-style, interconnect and heat-extraction components are co-architected considering the major challenges in 3D IC technology. In S3DC, the 3D interconnections provide greater routing capacity in both vertical and horizontal directions compared to conventional 3D ICs, which eliminates the routability issue in conventional 3D IC technology while enabling ultra-high density design and significant benefits over 2D. Also, the improved vertical routing capacity in S3DC is beneficial for achieving robust and high-density power delivery network (PDN) design while conventional 3D IC has design issues in PDN design due to limited routing resource in vertical direction. Additionally, the 3D gate-all-around transistor incorporating with 3D interconnect in S3DC enables significant SRAM design benefits and good tolerance of process variation compared to conventional 3D IC technology as well as 2D CMOS. The transistor-level (TR-L) monolithic 3D IC (M3D) is the state-of-the-art monolithic 3D technology which shows better benefits than other M3D approaches as well as the TSV-based 3D IC approach. The S3DC is evaluated in large-scale benchmark circuits with comparison to TR-L M3D as well as 2D CMOS. Skybridge yields up to 3x lower power against 2D with no routing congestion in benchmark circuits while TR-L M3D only has up-to 22% power saving with severe routing congestions in the design. The PDN design in S3DC show

High-performance Global Routing for Trillion-gate Systems-on-Chips.

Due to aggressive transistor scaling, modern-day CMOS circuits have continually increased in both complexity and productivity. Modern semiconductor designs have narrower and more resistive wires, thereby shifting the performance bottleneck to interconnect delay. These trends considerably impact timing closure and call for improvements in high-performance physical design tools to keep pace with the current state of IC innovation. As leading-edge designs may incorporate tens of millions of gates, algorithm and software scalability are crucial to achieving reasonable turnaround time. Moreover, with decreasing device sizes, optimizing traditional objectives is no longer sufficient. Our research focuses on (i) expanding the capabilities of standalone global routing, (ii) extending global routing for use in different design applications, and (iii) integrating routing within broader physical design optimizations and flows, e.g., congestion-driven placement. Our first global router relies on integer-linear programming (ILP), and can solve fairly large problem instances to optimality. Our second iterative global router relies on Lagrangian relaxation, where we relax the routing violation constraints to allowing routing overflow at a penalty. In both approaches, our desire is to give the router the maximum degree of freedom within a specified context. Empirically, both routers produce competitive results within a reasonable amount of runtime. To improve routability, we explore the incorporation of routing with placement, where the router estimates congestion and feeds this information to the placer. In turn, the emphasis on runtime is heightened, as the router will be invoked multiple times. Empirically, our placement-and-route framework significantly improves the final solution’s routability than performing the steps sequentially. To further enhance routability-driven placement, we (i) leverage incrementality to generate fast and accurate congestion maps, and (ii) develop several techniques to relieve cell-based and layout-based congestion. To broaden the scope of routing, we integrate a global router in a chip-design flow that addresses the buffer explosion problem.PHDComputer Science and EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98025/1/jinhu_1.pd

Graphics Processing Unit-Based Computer-Aided Design Algorithms for Electronic Design Automation

The electronic design automation (EDA) tools are a specific set of software that play important roles in modern integrated circuit (IC) design. These software automate the design processes of IC with various stages. Among these stages, two important EDA design tools are the focus of this research: floorplanning and global routing. Specifically, the goal of this study is to parallelize these two tools such that their execution time can be significantly shortened on modern multi-core and graphics processing unit (GPU) architectures. The GPU hardware is a massively parallel architecture, enabling thousands of independent threads to execute concurrently. Although a small set of EDA tools can benefit from using GPU to accelerate their speed, most algorithms in this field are designed with the single-core paradigm in mind. The floorplanning and global routing algorithms are among the latter, and difficult to render any speedup on the GPU due to their inherent sequential nature. This work parallelizes the floorplanning and global routing algorithm through a novel approach and results in significant speedups for both tools implemented on the GPU hardware. Specifically, with a complete overhaul of solution space and design space exploration, a GPU-based floorplanning algorithm is able to render 4-166X speedup, while achieving similar or improved solutions compared with the sequential algorithm. The GPU-based global routing algorithm is shown to achieve significant speedup against existing state-of-the-art routers, while delivering competitive solution quality. Importantly, this parallel model for global routing renders a stable solution that is independent from the level of parallelism. In summary, this research has shown that through a design paradigm overhaul, sequential algorithms can also benefit from the massively parallel architecture. The findings of this study have a positive impact on the efficiency and design quality of modern EDA design flow

On Robustness and Generalization of ML-Based Congestion Predictors to Valid and Imperceptible Perturbations

There is substantial interest in the use of machine learning (ML)-based techniques throughout the electronic computer-aided design (CAD) flow, particularly methods based on deep learning. However, while deep learning methods have achieved state-of-the-art performance in several applications, recent work has demonstrated that neural networks are generally vulnerable to small, carefully chosen perturbations of their input (e.g. a single pixel change in an image). In this work, we investigate robustness in the context of ML-based EDA tools -- particularly for congestion prediction. As far as we are aware, we are the first to explore this concept in the context of ML-based EDA. We first describe a novel notion of imperceptibility designed specifically for VLSI layout problems defined on netlists and cell placements. Our definition of imperceptibility is characterized by a guarantee that a perturbation to a layout will not alter its global routing. We then demonstrate that state-of-the-art CNN and GNN-based congestion models exhibit brittleness to imperceptible perturbations. Namely, we show that when a small number of cells (e.g. 1%-5% of cells) have their positions shifted such that a measure of global congestion is guaranteed to remain unaffected (e.g. 1% of the design adversarially shifted by 0.001% of the layout space results in a predicted decrease in congestion of up to 90%, while no change in congestion is implied by the perturbation). In other words, the quality of a predictor can be made arbitrarily poor (i.e. can be made to predict that a design is "congestion-free") for an arbitrary input layout. Next, we describe a simple technique to train predictors that improves robustness to these perturbations. Our work indicates that CAD engineers should be cautious when integrating neural network-based mechanisms in EDA flows to ensure robust and high-quality results.Comment: 7 pages, 7 figure

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations