L'arithmétique sur le tas

National audienceOn appelle un tas de bits une somme non évaluée de variable binaires, chacune pondérée par une puissance de 2. Par exemple, tous les polynômes à plusieurs variables peuvent s'exprimer comme un tas dont chaque variable est un ET logique des bits d'entrée. Cette représentation est pertinente car elle exprime le parallélisme au niveau du bit. La littérature sur les multiplieurs binaires montre comment construire des architectures efficaces qui calculent la valeurd'un tas de bits. Le présent article montre l'intérêt de revisiter un certain nombre d'opérateurs arithmétiques composés pour les exprimer comme des tas de bits

Integer Division by Constants: Optimal Bounds

The integer division of a numerator n by a divisor d gives a quotient q and a remainder r. Optimizing compilers accelerate software by replacing the division of n by d with the division of c * n (or c * n + c) by m for convenient integers c and m chosen so that they approximate the reciprocal: c/m ~= 1/d. Such techniques are especially advantageous when m is chosen to be a power of two and when d is a constant so that c and m can be precomputed. The literature contains many bounds on the distance between c/m and the divisor d. Some of these bounds are optimally tight, while others are not. We present optimally tight bounds for quotient and remainder computations

Author manuscript, published in "Dans Applied Reconfigurable Computing- Applied Reconfigurable Computing, Hong Kong: Hong-Kong" Table-based division by small integer constants

Abstract. Computing cores to be implemented on FPGAs may involve divisions by small integer constants in fixed or floating point. This article presents a family of architectures addressing this need. They are derived from a simple recurrence whose body can be implemented very efficiently as a look-up table that matches the hardware resources of the target FPGA. For instance, division of a 32-bit integer by the constant 3 may be implemented by a combinatorial circuit of 48 LUT6 on a Virtex-5. Other options are studied, including iterative implementations, and architectures based on embedded memory blocks. This technique also computes the remainder. An efficient implementation of the correctly rounded division of a floating-point constant by such a small integer is also presented.