75 research outputs found
Towards Very Large Scale Analog (VLSA): Synthesizable Frequency Generation Circuits.
Driven by advancement in integrated circuit design and fabrication technologies, electronic systems have become ubiquitous. This has been enabled powerful digital design tools that continue to shrink the design cost, time-to-market, and the size of digital circuits. Similarly, the manufacturing cost has been constantly declining for the last four decades due to CMOS scaling. However, analog systems have struggled to keep up with the unprecedented scaling of digital circuits. Even today, the majority of the analog circuit blocks are custom designed, do not scale well, and require long design cycles.
This thesis analyzes the factors responsible for the slow scaling of analog blocks, and presents a new design methodology that bridges the gap between traditional custom analog design and the modern digital design. The proposed methodology is utilized in implementation of the frequency generation circuits – traditionally considered analog systems. Prototypes covering two different applications were implemented. The first synthesized all-digital phase-locked loop was designed for 400-460 MHz MedRadio applications and was fabricated in a 65 nm CMOS process. The second prototype is an ultra-low power, near-threshold 187-500 kHz clock generator for energy harvesting/autonomous applications. Finally, a digitally-controlled oscillator frequency resolution enhancement technique is presented which allows reduction of quantization noise in ADPLLs without introducing spurs.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/109027/1/mufaisal_1.pd
A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems
Indo-ChinaAn agreement between Ho Chi Minh and the French (1946) made Vietnam a free state though fighting between parties erupted into the First Indochina War ending in May 1954.Vietnam. (2013). In Encyclopædia Britannica. Retrieved from http://school.eb.com/eb/article-52744GrayscaleForman Safety Negatives, Box
Modeling, Optimization and Testing for Analog/Mixed-Signal Circuits in Deeply Scaled CMOS Technologies
As CMOS technologies move to sub-100nm regions, the design and verification
for analog/mixed-signal circuits become more and more difficult due to the problems
including the decrease of transconductance, severe gate leakage and profound mismatches.
The increasing manufacturing-induced process variations and their impacts
on circuit performances make the already complex circuit design even more sophisticated
in the deeply scaled CMOS technologies. Given these barriers, efforts are
needed to ensure the circuits are robust and optimized with consideration of parametric
variations. This research presents innovative computer-aided design approaches
to address three such problems: (1) large analog/mixed-signal performance modeling
under process variations, (2) yield-aware optimization for complex analog/mixedsignal
systems and (3) on-chip test scheme development to detect and compensate
parametric failures.
The first problem focus on the efficient circuit performance evaluation with consideration
of process variations which serves as the baseline for robust analog circuit
design. We propose statistical performance modeling methods for two popular
types of complex analog/mixed-signal circuits including Sigma-Delta ADCs and
charge-pump PLLs. A more general performance modeling is achieved by employing
a geostatistics motivated performance model (Kriging model), which is accurate
and efficient for capturing stand-alone analog circuit block performances. Based on the generated block-level performance models, we can solve the more challenging
problem of yield-aware system optimization for large analog/mixed-signal systems.
Multi-yield pareto fronts are utilized in the hierarchical optimization framework so
that the statistical optimal solutions can be achieved efficiently for the systems. We
further look into on-chip design-for-test (DFT) circuits in analog systems and solve
the problems of linearity test in ADCs and DFT scheme optimization in charge-pump
PLLs. Finally a design example of digital intensive PLL is presented to illustrate the
practical applications of the modeling, optimization and testing approaches for large
analog/mixed-signal systems
A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems
This paper presents a modelling methodology for the top-down/bottom-up design of RF systems based on systematic use of VHDL-AMS models. The model interfaces are parameterizable and pin-accurate. The designer can choose to parameterize the models using performance specifications or device parameters back-annotated from the transistor-level implementation. The abstraction level used for the description of the respective analog/digital component behavior has been chosen to achieve a good trade-off between accuracy, fidelity, and simulation performance. These properties make the models suitable for different design tasks such as architectural exploration or overall system validation. This is demonstrated on a model of a binary FSK transmitter parameterized to meet very different target specifications. The achieved flexibility and systematic model documentation facilitate their reuse in other design projects
Clock Generator Circuits for Low-Power Heterogeneous Multiprocessor Systems-on-Chip
In this work concepts and circuits for local clock generation in low-power heterogeneous multiprocessor systems-on-chip (MPSoCs) are researched and developed. The targeted systems feature a globally asynchronous locally synchronous (GALS) clocking architecture and advanced power management functionality, as for example fine-grained ultra-fast dynamic voltage and frequency scaling (DVFS). To enable this functionality compact clock generators with low chip area, low power consumption, wide output frequency range and the capability for ultra-fast frequency changes are required. They are to be instantiated individually per core.
For this purpose compact all digital phase-locked loop (ADPLL) frequency synthesizers are developed. The bang-bang ADPLL architecture is analyzed using a numerical system model and optimized for low jitter accumulation. A 65nm CMOS ADPLL is implemented, featuring a novel active current bias circuit which compensates the supply voltage and temperature sensitivity of the digitally controlled oscillator (DCO) for reduced digital tuning effort. Additionally, a 28nm ADPLL with a new ultra-fast lock-in scheme based on single-shot phase synchronization is proposed.
The core clock is generated by an open-loop method using phase-switching between multi-phase DCO clocks at a fixed frequency. This allows instantaneous core frequency changes for ultra-fast DVFS without re-locking the closed loop ADPLL. The sensitivity of the open-loop clock generator with respect to phase mismatch is analyzed analytically and a compensation technique by cross-coupled inverter buffers is proposed.
The clock generators show small area (0.0097mm2 (65nm), 0.00234mm2 (28nm)), low power consumption (2.7mW (65nm), 0.64mW (28nm)) and they provide core clock frequencies from 83MHz to 666MHz which can be changed instantaneously. The jitter performance is compliant to DDR2/DDR3 memory interface specifications.
Additionally, high-speed clocks for novel serial on-chip data transceivers are generated. The ADPLL circuits have been verified successfully by 3 testchip implementations. They enable efficient realization of future low-power MPSoCs with advanced power management functionality in deep-submicron CMOS technologies.In dieser Arbeit werden Konzepte und Schaltungen zur lokalen Takterzeugung in heterogenen Multiprozessorsystemen (MPSoCs) mit geringer Verlustleistung erforscht und entwickelt. Diese Systeme besitzen eine global-asynchrone lokal-synchrone Architektur sowie Funktionalität zum Power Management, wie z.B. das feingranulare, schnelle Skalieren von Spannung und Taktfrequenz (DVFS). Um diese Funktionalität zu realisieren werden kompakte Taktgeneratoren benötigt, welche eine kleine Chipfläche einnehmen, wenig Verlustleitung aufnehmen, einen weiten Bereich an Ausgangsfrequenzen erzeugen und diese sehr schnell ändern können.
Sie sollen individuell pro Prozessorkern integriert werden. Dazu werden kompakte volldigitale Phasenregelkreise (ADPLLs) entwickelt, wobei eine bang-bang ADPLL Architektur numerisch modelliert und für kleine Jitterakkumulation optimiert wird. Es wird eine 65nm CMOS ADPLL implementiert, welche eine neuartige Kompensationsschlatung für den digital gesteuerten Oszillator (DCO) zur Verringerung der Sensitivität bezüglich Versorgungsspannung und Temperatur beinhaltet. Zusätzlich wird eine 28nm CMOS ADPLL mit einer neuen Technik zum schnellen Einschwingen unter Nutzung eines Phasensynchronisierers realisiert. Der Prozessortakt wird durch ein neuartiges Phasenmultiplex- und Frequenzteilerverfahren erzeugt, welches es ermöglicht die Taktfrequenz sofort zu ändern um schnelles DVFS zu realisieren.
Die Sensitivität dieses Frequenzgenerators bezüglich Phasen-Mismatch wird theoretisch analysiert und durch Verwendung von kreuzgekoppelten Taktverstärkern kompensiert. Die hier entwickelten Taktgeneratoren haben eine kleine Chipfläche (0.0097mm2 (65nm), 0.00234mm2 (28nm)) und Leistungsaufnahme (2.7mW (65nm), 0.64mW (28nm)). Sie stellen Frequenzen von 83MHz bis 666MHz bereit, welche sofort geändert werden können. Die Schaltungen erfüllen die Jitterspezifikationen von DDR2/DDR3 Speicherinterfaces. Zusätzliche können schnelle Takte für neuartige serielle on-Chip
Verbindungen erzeugt werden. Die ADPLL Schaltungen wurden erfolgreich in 3 Testchips erprobt. Sie ermöglichen die effiziente Realisierung von zukünftigen MPSoCs mit Power Management in modernsten CMOS Technologien
Applications of MATLAB in Science and Engineering
The book consists of 24 chapters illustrating a wide range of areas where MATLAB tools are applied. These areas include mathematics, physics, chemistry and chemical engineering, mechanical engineering, biological (molecular biology) and medical sciences, communication and control systems, digital signal, image and video processing, system modeling and simulation. Many interesting problems have been included throughout the book, and its contents will be beneficial for students and professionals in wide areas of interest
Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters
Analog-to-digital converters (ADCs) are key design blocks in
state-of-art image, capacitive, and biomedical sensing applications.
In these sensing applications, algorithmic ADCs are the preferred
choice due to their high resolution and low area advantages.
Algorithmic ADCs are based on the same operating principle as that
of pipelined ADCs. Unlike pipelined ADCs where the residue is
transferred to the next stage, an N-bit algorithmic ADC utilizes the
same hardware N-times for each bit of resolution. Due to the
cyclic nature of algorithmic ADCs, many of the low power techniques
applicable to pipelined ADCs cannot be
directly applied to algorithmic ADCs. Consequently, compared to those of
pipelined ADCs, the traditional implementations of algorithmic ADCs are
power inefficient.
This thesis presents two novel energy efficient techniques for algorithmic
ADCs. The first technique modifies the capacitors' arrangement of a
conventional flip-around configuration and amplifier sharing
technique, resulting in a low power and low area design solution. The
other technique is based on the unit
multiplying-digital-to-analog-converter approach. The proposed
approach exploits the power saving advantages of capacitor-shared technique
and capacitor-scaled technique. It is shown that, compared to
conventional techniques, the proposed techniques reduce the
power consumption of algorithmic ADCs by more than 85\%.
To verify the effectiveness of such approaches, two
prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are
implemented in a 130-nm CMOS process. Detailed design considerations
are discussed as well as the simulation and measurement results. According to the
simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step,
making them some of the most power efficient ADCs to date
Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters
Analog-to-digital converters (ADCs) are key design blocks in
state-of-art image, capacitive, and biomedical sensing applications.
In these sensing applications, algorithmic ADCs are the preferred
choice due to their high resolution and low area advantages.
Algorithmic ADCs are based on the same operating principle as that
of pipelined ADCs. Unlike pipelined ADCs where the residue is
transferred to the next stage, an N-bit algorithmic ADC utilizes the
same hardware N-times for each bit of resolution. Due to the
cyclic nature of algorithmic ADCs, many of the low power techniques
applicable to pipelined ADCs cannot be
directly applied to algorithmic ADCs. Consequently, compared to those of
pipelined ADCs, the traditional implementations of algorithmic ADCs are
power inefficient.
This thesis presents two novel energy efficient techniques for algorithmic
ADCs. The first technique modifies the capacitors' arrangement of a
conventional flip-around configuration and amplifier sharing
technique, resulting in a low power and low area design solution. The
other technique is based on the unit
multiplying-digital-to-analog-converter approach. The proposed
approach exploits the power saving advantages of capacitor-shared technique
and capacitor-scaled technique. It is shown that, compared to
conventional techniques, the proposed techniques reduce the
power consumption of algorithmic ADCs by more than 85\%.
To verify the effectiveness of such approaches, two
prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are
implemented in a 130-nm CMOS process. Detailed design considerations
are discussed as well as the simulation and measurement results. According to the
simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step,
making them some of the most power efficient ADCs to date
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