SystemC Model of Hierarchical Network-on-Chip for System-Level On-Chip Multi-Core Platform

System-Level Modeling is one of the key tools to speed up the process of design space exploration. Open source system level design tool is the solution for SMEs to get maximum benefit out of system level modeling in affordable range. SystemC is a C++ library extension that is used for open source system level modeling. In this thesis, a NoC based on hierarchical NoC for Ninesilica is modeled using SystemC. The Ninesilica multi-core platform that is developed at Department of Computer System in Tampere University of Technology. The system level NoC model is able to simulate the communication network with several number of nodes and data packets. The modeled NoC is able to give useful information regarding to delay, data packet buffering and number of clock cycles required to transfer all the data packets. The user can also be able to get information about the position of any data packet at any clock cycle in the network. The behavior of the communication network is analyzed with different number of nodes and several network configurations. The data load is also varied in order to verify that the NoC model is working properly. The NoC model successfully completed all the tests and gives the results as expected. The NoC model is able to buffer, transmit, and receive data packets without any loss of data packets. The NoC model can be configured and re-configured. The simulation results are written to a text file. Several comparisons between different network topologies with variable data load is also made and some conclusions based on those results are made. /Kir1