13,430 research outputs found

    Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm

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    A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 μm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e Innovación TEC2009-08447Junta de Andalucía TIC-0281

    Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

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    This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI

    Magnetic Doppler imaging of alpha^2 Canum Venaticorum in all four Stokes parameters. Unveiling the hidden complexity of stellar magnetic fields

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    Strong organized magnetic fields have been studied in the upper main sequence chemically peculiar stars for more than half a century. However, only recently have observational methods and numerical techniques become sufficiently mature to allow us to record and interpret high-resolution four Stokes parameter spectra, leading to the first assumption-free magnetic field models of these stars. Here we present a detailed magnetic Doppler imaging analysis of the spectropolarimetric observations of the prototypical magnetic Ap star alpha^2 CVn. The surface abundance distributions of Fe and Cr and a full vector map of the stellar magnetic field are reconstructed in a self-consistent inversion using our state-of-the-art magnetic Doppler imaging code Invers10. We succeeded in reproducing most of the details of the available spectropolarimetric observations of alpha^2 CVn with a magnetic map which combines a global dipolar-like field topology with localized spots of higher field intensity. We demonstrate that these small-scale magnetic structures are inevitably required to fit the linear polarization spectra; however, their presence cannot be inferred from the Stokes I and V observations alone. Our magnetic Doppler imaging analysis of alpha^2 CVn and previous results for 53 Cam support the view that the upper main sequence stars can harbour fairly complex surface magnetic fields which resemble oblique dipoles only at the largest spatial scales. Spectra in all four Stokes parameters are absolutely essential to unveil and meaningfully characterize this field complexity in Ap stars. We therefore suggest that understanding magnetism of stars in other parts of the H-R diagram is similarly incomplete without investigation of their linear polarization spectra.Comment: 16 pages, 12 figures; Accepted for publication by Astronomy & Astrophysic

    Technology Mapping for Circuit Optimization Using Content-Addressable Memory

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    The growing complexity of Field Programmable Gate Arrays (FPGA's) is leading to architectures with high input cardinality look-up tables (LUT's). This thesis describes a methodology for area-minimizing technology mapping for combinational logic, specifically designed for such FPGA architectures. This methodology, called LURU, leverages the parallel search capabilities of Content-Addressable Memories (CAM's) to outperform traditional mapping algorithms in both execution time and quality of results. The LURU algorithm is fundamentally different from other techniques for technology mapping in that LURU uses textual string representations of circuit topology in order to efficiently store and search for circuit patterns in a CAM. A circuit is mapped to the target LUT technology using both exact and inexact string matching techniques. Common subcircuit expressions (CSE's) are also identified and used for architectural optimization---a small set of CSE's is shown to effectively cover an average of 96% of the test circuits. LURU was tested with the ISCAS'85 suite of combinational benchmark circuits and compared with the mapping algorithms FlowMap and CutMap. The area reduction shown by LURU is, on average, 20% better compared to FlowMap and CutMap. The asymptotic runtime complexity of LURU is shown to be better than that of both FlowMap and CutMap

    Synthesizing Minimum Total Expansion Topologies for Reconfigurable Interconnection Networks

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    The Performance of a parallel algorithm depends in part on how the interconnection topology of the target parallel system matches the communication patterns of the algorithm. We describe how to generate a topology for a network that can be configured into and r-regular topology. The topology generated has small total expansion with respect to a given task graph. The expansion of an edge in a task graph is the length of the shortest path that the edge maps to in the processor graph. The algorithm used to generate the topologies is analyzed and its average case behavior is determined. In addition, this synthesis method is compared to the conventional approach of mapping a task graph onto a fixed processor topology

    Noise Processing by MicroRNA-Mediated Circuits: the Incoherent Feed-Forward Loop, Revisited

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    The intrinsic stochasticity of gene expression is usually mitigated in higher eukaryotes by post-transcriptional regulation channels that stabilise the output layer, most notably protein levels. The discovery of small non-coding RNAs (miRNAs) in specific motifs of the genetic regulatory network has led to identifying noise buffering as the possible key function they exert in regulation. Recent in vitro} and in silico studies have corroborated this hypothesis. It is however also known that miRNA-mediated noise reduction is hampered by transcriptional bursting in simple topologies. Here, using stochastic simulations validated by analytical calculations based on van Kampen's expansion, we revisit the noise-buffering capacity of the miRNA-mediated Incoherent Feed Forward Loop (IFFL), a small module that is widespread in the gene regulatory networks of higher eukaryotes, in order to account for the effects of intermittency in the transcriptional activity of the modulator gene. We show that bursting considerably alters the circuit's ability to control static protein noise. By comparing with other regulatory architectures, we find that direct transcriptional regulation significantly outperforms the IFFL in a broad range of kinetic parameters. This suggests that, under pulsatile inputs, static noise reduction may be less important than dynamical aspects of noise and information processing in characterising the performance of regulatory elements.Comment: 25 pages (Main Text and Supplementary Information), 5 figure
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