2 research outputs found

    Symbolic computation and representation of deadlock avoidance policies for complex resource allocation systems with application to multithreaded software

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    In our recent work, we proposed a series of binary decision diagram (BDD-) based approaches for developing the maximally permissive deadlock avoidance policy (DAP) for a class of complex resource allocation systems (RAS). In this paper, (i) we extend these approaches by introducing a procedure that generates a set of comprehensible \u27guard\u27 predicates to represent the resulting DAP, and (ii) we customize them to the problem of deadlock avoidance in shared-memory multithreaded software, that has been previously addressed by the Gadara project. In the context of this last application, the generated guards can be instrumented directly into the source code of the underlying software threads, providing, thus, a very efficient and natural representation of the target policy. At the same time, by integrating the representational and computational strengths of symbolic computation, the presented approach can support the computation of the maximally permissive DAP for RAS corresponding to problem instances of even larger scale and complexity than those addressed in the current literature

    Symbolic Supervisory Control of Resource Allocation Systems

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    <p>Supervisory control theory (SCT) is a formal model-based methodology for verification and synthesis of supervisors for discrete event systems (DES). The main goal is to guarantee that the closed-loop system fulfills given specifications. SCT has great promise to assist engineers with the generation of reliable control functions. This is, for instance, beneficial to manufacturing systems where both products and production equipment might change frequently.</p> <p>The industrial acceptance of SCT, however, has been limited for at least two reasons: (i) the analysis of DES involves an intrinsic difficulty known as the state-space explosion problem, which makes the explicit enumeration of enormous state-spaces for industrial systems intractable; (ii) the synthesized supervisor, represented as a deterministic finite automaton (FA) or an extended finite automaton (EFA), is not straightforward to implement in an industrial controller.</p> <p>In this thesis, to address the aforementioned issues, we study the modeling, synthesis and supervisor representation of DES using binary decision diagrams (BDDs), a compact data structure for representing DES models symbolically. We propose different kinds of BDD-based algorithms for exploring the symbolically represented state-spaces in an effort to improve the abilities of existing supervisor synthesis approaches to handle large-scale DES and represent the obtained supervisors appropriately.</p> <p>Following this spirit, we bring the efficiencies of BDD into a particular DES application domain -- deadlock avoidance for resource allocation systems (RAS) -- a problem that arises in many technological systems including flexible manufacturing systems and multi-threaded software. We propose a framework for the effective and computationally efficient development of the maximally permissive deadlock avoidance policy (DAP) for various RAS classes. Besides the employment of symbolic computation, special structural properties that are possessed by RAS are utilized by the symbolic algorithms to gain additional efficiencies in the computation of the sought DAP. Furthermore, to bridge the gap between the BDD-based representation of the target DAP and its actual industrial realization, we extend this work by introducing a procedure that generates a set of "guard" predicates to represent the resulting DAP.</p> <p>The work presented in this thesis has been implemented in the SCT tool Supremica. Computational benchmarks have manifested the superiority of the proposed algorithms with respect to the previously published results. Hence, the work holds a strong potential for providing robust, practical and efficient solutions to a broad range of supervisory control and deadlock avoidance problems that are experienced in the considered DES application domain.</p
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