A Dual Gate Spin Field Effect Transistor With Very Low Switching Voltage and Large ON-to-OFF Conductance Ratio

We propose and analyze a novel dual-gate Spin Field Effect Transistor (SpinFET) with half-metallic ferromagnetic source and drain contacts. The transistor has two gate pads that can be biased independently. It can be switched ON or OFF with a few mV change in the differential bias between the two pads, resulting in extremely low dynamic power dissipation during switching. The ratio of ON to OFF conductance remains fairly large (~ 60) up to a temperature of 10 K. This device also has excellent inverter characteristics, making it attractive for applications in low power and high density Boolean logic circuits

Electron Spin for Classical Information Processing: A Brief Survey of Spin-Based Logic Devices, Gates and Circuits

In electronics, information has been traditionally stored, processed and communicated using an electron's charge. This paradigm is increasingly turning out to be energy-inefficient, because movement of charge within an information-processing device invariably causes current flow and an associated dissipation. Replacing charge with the "spin" of an electron to encode information may eliminate much of this dissipation and lead to more energy-efficient "green electronics". This realization has spurred significant research in spintronic devices and circuits where spin either directly acts as the physical variable for hosting information or augments the role of charge. In this review article, we discuss and elucidate some of these ideas, and highlight their strengths and weaknesses. Many of them can potentially reduce energy dissipation significantly, but unfortunately are error-prone and unreliable. Moreover, there are serious obstacles to their technological implementation that may be difficult to overcome in the near term. This review addresses three constructs: (1) single devices or binary switches that can be constituents of Boolean logic gates for digital information processing, (2) complete gates that are capable of performing specific Boolean logic operations, and (3) combinational circuits or architectures (equivalent to many gates working in unison) that are capable of performing universal computation.Comment: Topical Revie

A Digital Switch and Femto-Tesla Magnetic Field Sensor Based on Fano Resonance in a Spin Field Effect Transistor

We show that a Spin Field Effect Transistor, realized with a semiconductor quantum wire channel sandwiched between half-metallic ferromagnetic contacts, can have Fano resonances in the transmission spectrum. These resonances appear because the ferromagnets are half-metallic, so that the Fermi level can be placed above the majority but below the minority spin band. In that case, the majority spins will be propagating, but the minority spins will be evanescent. At low temperatures, the Fano resonances can be exploited to implement a digital binary switch that can be turned on or off with a very small gate voltage swing of few tens of microvolts, leading to extremely small dynamic power dissipation during switching. An array of 500,000 x 500,000 such transistors can detect ultrasmall changes in a magnetic field with a sensitivity of 1 femto-Tesla/sqrt{Hz}, if each transistor is biased near a Fano resonance

Nanomagnetic Boolean Logic -- The Tempered (and Realistic) Vision

The idea of nanomagnetic Boolean logic was advanced more than two decades ago. It envisaged the use of nanomagnets with two stable magnetization orientations as the primitive binary switch for implementing logic gates and ultimately combinational/sequential circuits. Enthusiastic proclamations of how nanomagnetic logic will eclipse traditional (transistor-based) logic circuits proliferated the applied physics literature. Two decades later there is not a single viable nanomagnetic logic chip in sight, let alone one that is a commercial success. In this perspective article, I offer my reasons on why this has come to pass. I present a realistic and tempered vision of nanomagnetic logic, pointing out many misconceptions about this paradigm, flaws in some proposals that appeared in the literature, shortcomings, and likely pitfalls that might stymie progress in this field.Comment: Accepted in IEEE Acces

Energy efficient hybrid computing systems using spin devices

Emerging spin-devices like magnetic tunnel junctions (MTJ\u27s), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ∼20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode\u27 processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ∼100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters