Sum-of-Product Architectures Computing Just Right

International audienceMany digital filters and signal-processing transforms can be expressed as a sum of products with constants (SPC). This paper addresses the automatic construction of low-precision, but high accuracy SPC architectures: these architectures are specified as last-bit accurate with respect to a mathematical definition. In other words, they behave as if the computation was performed with infinite accuracy, then rounded only once to the low-precision output format. This eases the task of porting double-precision code (e.g. Matlab) to low-precision hardware or FPGA. The paper further discusses the construction of the most efficient architectures obeying such a specification, introducing several architectural improvements to this purpose. This approach is demonstrated in a generic, open-source architecture generator tool built upon the FloPoCo framework. It is evaluated on Finite Impulse Response filters for the ZigBee protocol

Realizing arbitrary-precision modular multiplication with a fixed-precision multiplier datapath

Within the context of cryptographic hardware, the term scalability refers to the ability to process operands of any size, regardless of the precision of the underlying data path or registers. In this paper we present a simple yet effective technique for increasing the scalability of a fixed-precision Montgomery multiplier. Our idea is to extend the datapath of a Montgomery multiplier in such a way that it can also perform an ordinary multiplication of two n-bit operands (without modular reduction), yielding a 2n-bit result. This conventional (nxn->2n)-bit multiplication is then used as a “sub-routine” to realize arbitrary-precision Montgomery multiplication according to standard software algorithms such as Coarsely Integrated Operand Scanning (CIOS). We show that performing a 2n-bit modular multiplication on an n-bit multiplier can be done in 5n clock cycles, whereby we assume that the n-bit modular multiplication takes n cycles. Extending a Montgomery multiplier for this extra functionality requires just some minor modifications of the datapath and entails a slight increase in silicon area

Three-dimensional surface codes: Transversal gates and fault-tolerant architectures

One of the leading quantum computing architectures is based on the two-dimensional (2D) surface code. This code has many advantageous properties such as a high error threshold and a planar layout of physical qubits where each physical qubit need only interact with its nearest neighbours. However, the transversal logical gates available in 2D surface codes are limited. This means that an additional (resource intensive) procedure known as magic state distillation is required to do universal quantum computing with 2D surface codes. Here, we examine three-dimensional (3D) surface codes in the context of quantum computation. We introduce a picture for visualizing 3D surface codes which is useful for analysing stacks of three 3D surface codes. We use this picture to prove that the $CZ$ and $CCZ$ gates are transversal in 3D surface codes. We also generalize the techniques of 2D surface code lattice surgery to 3D surface codes. We combine these results and propose two quantum computing architectures based on 3D surface codes. Magic state distillation is not required in either of our architectures. Finally, we show that a stack of three 3D surface codes can be transformed into a single 3D color code (another type of quantum error-correcting code) using code concatenation.Comment: 23 pages, 24 figures, v2: published versio