One dimensional transport in silicon nanowire junction-less field effect transistors

Junction-less nanowire transistors are being investigated to solve short channel effects in future CMOS technology. Here we demonstrate 8 nm diameter silicon nanowire junction-less transistors with metallic doping densities which demonstrate clear 1D electronic transport characteristics. The 1D regime allows excellent gate modulation with near ideal subthreshold slopes, on- to off-current ratios above 108 and high on-currents at room temperature. Universal conductance scaling as a function of voltage and temperature similar to previous reports of Luttinger liquids and Coulomb gap behaviour at low temperatures suggests that many body effects including electron-electron interactions are important in describing the electronic transport. This suggests that modelling of such nanowire devices will require 1D models which include many body interactions to accurately simulate the electronic transport to optimise the technology but also suggest that 1D effects could be used to enhance future transistor performance

Improving the Readout of Semiconducting Qubits

Semiconducting qubits are a promising platform for quantum computers. In particular, silicon spin qubits have made a number of advancements recently including long coherence times, high-fidelity single-qubit gates, two-qubit gates, and high-fidelity readout. However, all operations likely require improvement in fidelity and speed, if possible, to realize a quantum computer. Readout fidelity and speed, in general, are limited by circuit challenges centered on extracting low signal from a device in a dilution refrigerator connected to room temperature amplifiers by long coaxial cables with relatively high capacitance. Readout fidelity specifically is limited by the time it takes to reliably distinguish qubit states relative to the characteristic decay time of the excited state, T1. This dissertation explores the use of heterojunction bipolar transistor (HBT) circuits to amplify the readout signal of silicon spin qubits at cryogenic temperatures. The cryogenic amplification approach has numerous advantages including low implementation overhead, low power relative to the available cooling power, and high signal gain at the mixing chamber stage leading to around a factor of ten speedup in readout time for a similar signal-to-noise ratio. The faster readout time generally increases fidelity, since it is much faster than the T1 time. Two HBT amplification circuits have been designed and characterized. One design is a low-power, base-current biased configuration with non-linear gain (CB-HBT), and the second is a linear-gain, AC-coupled configuration (AC-HBT). They can operate at powers of 1 and 10 μW, respectfully, and not significantly heat electrons. The noise spectral density referred to the input for both circuits is around 15 to 30 fA/√Hz, which is low compared to previous cases such as the dual-stage, AC-coupled HEMT circuit at ~ 70 fA/√Hz. Both circuits achieve charge sensitivity between 300 and 400 μe/√Hz, which approaches the best alternatives (e.g., RF-SET at ~ 140 μe/√Hz) but with much less implementation overhead. For the single-shot latched charge readout performed, both circuits achieve high-fidelity readout in times \u3c 10 μs with bit error rates \u3c 10-3, which is a great improvement over previous work at \u3e 70 μs. The readout speed-up in principle also reduces the production of errors due to excited state relaxation by a factor of ~ 10. All of these results are possible with relatively simple, low-power transistor circuits which can be mounted close to the qubit device at the mixing chamber stage of the dilution refrigerator