Strength-Reduced Parallel Chien Search Architecture for Strong BCH Codes

The Chien search process is the most complex block in the decoding of Bose-Chaudhuri-Hochquenghem (BCH) codes. Since the BCH codes conduct the bit-by-bit error correction, they often need a parallel implementation for high throughput applications. The parallel implementation obviously needs much increased hardware. In this paper, we propose a strength reduced architecture for the parallel Chien search process. The proposed method transforms the expensive modulo-f(x) multiplications into shift operations, by which not only the hardware for multiplications but also that for additions are much reduced. One example shows that the hardware complexity is reduced by 90% in the implementation of binary BCH (8191, 7684, 39) code with the parallel factor of 64. Consequently, it is possible to achieve a speedup of 64 with only 13 times of the hardware complexity when compared with the serial processing

Characterization of BCH codes and its use in M2M healthcare applications

[ABSTRACT] Machine-to-Machine (M2M) applications require reliable communications, especially in the medical field, at low-energy consumption to extend the battery life of the sensors. This fact makes BCH codes an interesting option for IEEE 802.15.6 communications since their algebraic nature permit them to obtain the positions of the erroneous bits with mathematical equations of reduced complexity. Moreover, the decoder can be enhanced to save energy through several ways that are exposed in the project. M2M networks support a large number of interconnected devices. Given that the access to the gateways is through slotted protocols the increase in the demand lead to a reduction in the time-slot. Therefore is necessary to guarantee the reliability of the transmitted information as fast as possible. In addition medical applications are delay non-tolerant since a delay in the decisions could cause fatal consequences. In this project BCH encoding and decoding algorithms will be implemented in a motta to determine the reduction of time that provides each improvement in the algorithm.[RESUMEN] Las aplicaciones Machine-to-Machine (M2M) exigen comunicaciones seguras, especialmente en las médicas, y un bajo consumo de energía para alargar la vida de las baterías. Esto hace que los códigos BCH sean una buena opción para las comunicaciones IEEE 802.15.6 ya que su naturaleza algebraica les permite obtener las posiciones de los bits erróneos a partir de ecuaciones matemáticas poco complejas. Además, el decodificador puede ser mejorado para ahorrar energía de varias maneras las cuales se exponen en el proyecto. Las redes M2M soportan un gran número de dispositivos interconectados. Dado que el acceso a las puertas de enlace se realiza mediante protocolos ranurados, el incremento de peticiones de acceso conlleva a la reducción del tiempo de ranura. Por tanto es necesario garantizar la validez de la información transmitida tan rápido como sea posible. Además, las aplicaciones médicas no son tolerantes a los retrasos ya que en tal caso las consecuencias podrían ser fatales. En este proyecto los algoritmos de codificación y decodificación BCH serán implementados en motas para determinar la reducción de tiempo que aporta cada mejora en el algoritmo

Error Characterization and Correction Techniques for Reliable STT-RAM Designs

The concerns on the continuous scaling of mainstream memory technologies have motivated tremendous investment to emerging memories. Being a promising candidate, spin-transfer torque random access memory (STT-RAM) offers nanosecond access time comparable to SRAM, high integration density close to DRAM, non-volatility as Flash memory, and good scalability. It is well positioned as the replacement of SRAM and DRAM for on-chip cache and main memory applications. However, reliability issue continues being one of the major challenges in STT-RAM memory designs due to the process variations and unique thermal fluctuations, i.e., the stochastic resistance switching property of magnetic devices. In this dissertation, I decoupled the reliability issues as following three-folds: First, the characterization of STT-RAM operation errors often require expensive Monte-Carlo runs with hybrid magnetic-CMOS simulation steps, making it impracticable for architects and system designs; Second, the state of the art does not have sufficiently understanding on the unique reliability issue of STT-RAM, and conventional error correction codes (ECCs) cannot efficiently handle such errors; Third, while the information density of STT-RAM can be boosted by multi-level cell (MLC) design, the more prominent reliability concerns and the complicated access mechanism greatly limit its applications in memory subsystems. Thus, I present a novel through solution set to both characterize and tackle the above reliability challenges in STT-RAM designs. In the first part of the dissertation, I introduce a new characterization method that can accurately and efficiently capture the multi-variable design metrics of STT-RAM cells; Second, a novel ECC scheme, namely, content-dependent ECC (CD-ECC), is developed to combat the characterized asymmetric errors of STT-RAM at 0->1 and 1->0 bit flipping's; Third, I present a circuit-architecture design, namely state-restricted multi-level cell (SR-MLC) STT-RAM design, which simultaneously achieves high information density, good storage reliability and fast write speed, making MLC STT-RAM accessible for system designers under current technology node. Finally, I conclude that efficient robust (or ECC) designs for STT-RAM require a deep holistic understanding on three different levels-device, circuit and architecture. Innovative ECC schemes and their architectural applications, still deserve serious research and investigation in the near future