Strain-Reduction Induced Rise in Channel Temperature at Ohmic Contacts of GaN HEMTs

Operating temperature distributions in AlGaN/GaN gateless and gated devices are characterized and analyzed using the InfraScope temperature mapping system. For the first time, a substantial rise of channel temperature at the inner ends of ohmic contacts has been observed. Synchrotron radiation based high-resolution X-ray diffraction technique combined with drift -diffusion simulations show that strain reduction at the vicinity of ohmic contacts increases electric fi eld at these locations, resulting in the rise of lattice temperature. The thermal coupling of a high conductive tensile region at the contacts to a low conductive channel region is an origin of the temperature rise observed in both short- and long-channel gateless devices

Advanced GaN HEMT technology for millimetre-wave amplifiers

Gallium Nitride (GaN)-based High-Electron-Mobility Transistor (HEMT) technology is a breakthrough innovation in the semiconductor industry, offering high-frequency and high-power performance capabilities. GaN HEMTs are widely used in power electronics, wireless communication systems, and radar applications over the past two decades. The key advantages of GaN HEMTs to produce heterojunctions to larger bandgap materials Aluminium Gallium Nitride (AlGaN) and the heterostructure results in the formation of the 2- dimensional electron gas (2DEG) which exhibits high electron mobilities of upto 2000 cm²/V.s and high saturation velocity of 2×10⁷ cm/s, resulting in high switching speeds and power densities. Due to its wide bandgap of 3.4 eV, it also allows exceptionally high breakdown fields of 3.3 MV/cm. In this thesis, the focus is on the major challenges in the development of GaN HEMT technology including achieving a low resistance ohmic contact, reducing self-heating, and improving device high frequency performance. Due to the wide bandgap of III-nitride semiconductors, achieving low-resistance Ohmic contact resistance is difficult. Recessing the Ohmic region prior to metallization is a typical approach to lowering the contact resistance. The contact resistance is often minimised by optimising factors such as recess depth, anneal temperature, and metal stack design. In this work, the three approaches involving the recessing of the ohmic region were evaluated. The Ohmic contact area was recessed in patterns similar to a chess board, vertical recessed stripes, and horizontal recessed strips. The two different recess etch depths, shallow and deep etch depths of 9 nm and 30 nm, respectively, were investigate. The lowest contact resistance of 0.32 Ω.mm (compared to 0.59 Ω.mm for a conventional non-recessed Ohmic contact) was observed for a deep horizontal patterned structure. The results also indicate that a highly reproducible process. The other major issue to address was to reduce the impact of device self-heating by effective heat distribution and dissipation. A novel thermal management technique was proposed, and the preliminary results are promising. It exploits the very thin epitaxial layer stack of a buffer-less GaN-on-SiC HEMT structure. III-V nitride material is etched and removed from around the active device area and the Au bond pad electrodes sit directly on the SiC substrate, providing a route for thermal dissipation from the active device to the substrate. This approach was demonstrated to reduce device self-heating and to improve the current density of the device. We fabricated and compared the performance of devices fabricated on the buffer-free and conventional GaN HEMTs. For identically sized 2-μm gate long, two-finger 2 × 50 μm gate width device with a gate to drain spacing of 3 m, the conventional devices broke down at 186 V while for the buffer-free structure, it was over 200 V (above the measurement capability of our equipment). The maximum drain current density of ~631 mA/mm and ~ 686 mA/mm biased at VGS = 1 V for the two-finger 2 × 50 μm gate wide for buffer free and conventional GaN structure, respectively. The buffer free and conventional GaN structure devices were measured to determine their maximum cut-off frequency (fT) and maximum oscillation frequency (fmax) when biased at VDS = 15V. The lower gate leakage currents were observed for the fabricated buffer-free AlGaN/GaN HEMT device as compared to conventional GaN HEMTs 197μA and 260μA, respectively. Also, the buffer free device, which had two fingers each measuring 2x200 μm, yielded measurements of 4.6 GHz for fT and 9.8 GHz for fmax. The conventional GaN device, also with two fingers each measuring 2x200 μm, was tested and resulted in measurements of 6.3 GHz for fT and 14.7 GHz for fmax. These results demonstrate the high quality of the buffer-free GaN heterostructure despite the absence of thick transition layers as currently used in the conventional GaN HEMTs. This indicates that the "buffer-free" design has the potential to be useful for millimetre wave applications in the future. This thesis also describes the fabrication and characterisation of a 100 nm footprint Ni/Au-based T-gate HEMT, 2x25 μm gate width, 1.5 μm drain source spacing, 100nm Si₃N₄ passivation layer thickness and device exhibit quite high peak currents of 805mA/mm and peak transconductance value of 246 mS/mm due to the low thermal boundary resistance on this buffer free epilayer wafer. The breakdown voltage was measured 47 Volts. Yielding a cut-off frequency fT of 87 GHz and maximum oscillation frequency fₘₐₓ of 143 GHz. We have developed a method for fabricating a T-shaped gate for sub 100nm gate foot length. The 100 nm length results in robustness, repeatable and has a high yield. Our findings indicate that this gate design could be beneficial for AlGaN/GaN buffer-free HEMTs used in millimetre wave frequency applications

Reliability Characterisation of III-Nitrides Based Devices for Technology Development

III-nitrides based devices are considered as outstanding options for a range of extremely relevant applications. These devices can significantly improve the efficiency of high-power switching appliations. They are predicted to dominate applications in the low carbon economy. In recent years, these devices have been steadily improved and each year new record performances have been reported. Regardless of the superior performance of III-nitrides based devices, and particularly AlGaN/GaN high electron mobility transistors (HEMTs), achieving reliability at the same time as the high performance that the device boasts is a factor that is holding back widespread commercial and industrial development. Recoverable degradation (e.g. current collapse and on-resistance) and unrecoverable degradation (e.g. access resistance of contacts, and gate leakage current) persist to be limiting reliability factors. The mechanisms contributing towards performance and reliability degradation of AlGaN/GaN HEMTs, namely self-heating, charge trapping and strain, are required to be minimised; an important step before large-scale deployment can be attained. The strong coupling of these degradation mechanisms, under normal device operation, makes the quantitative contribution of each mechanism indistinct due to the lack of standard characterisation techniques. In this Thesis, the impact of the source/drain (S/D) and gate terminals of an AlGaN/GaN HEMT on its thermal management was investigated. Using Infrascope measurements, a substantial increase in temperature and resistance at the inner ends of the S/D contacts was observed. High-resolution X-ray diffraction technique combined with drift-diffusion (DD) simulations showed that strain reduction at the vicinity of S/D contacts is the origin of temperature rise. The strain reduction was also observed below the metal gate. Through electro-thermal simulations, the electrical stress on Ohmic contacts was shown to reduce the strain; leading to the inverse/converse piezoelectric effect. A new parametric technique was developed to decouple the mechanisms constituting device degradation in AlGaN/GaN HEMTs under normal device operation, namely self-heating and charge trapping. Both source (IS) and drain (ID) transient currents were used under various biasing conditions to analyse charge trapping behaviour. Two types of charge trapping mechanisms have been identified: (i) bulk trapping occurring on a time scale of 1 ms. Through monitoring the difference between I_S and I_D, bulk trapping time constant is shown to be independent of V_DS and V_GS. Also, V_GS is found to have no effect on the bulk trap density. Surface trapping is found to have a much greater impact on slow degradation when compared to self-heating and bulk trapping. At a short time scale (1ms), the dynamic ON resistance degradation is limited mainly by surface trapping accumulation and redistribution. Using the understanding of the degradation mechanism behaviour and origins, optimisations to the Ohmic and Schottky contacts as well as a new AlGaN/GaN HEMT architecture were proposed. In an attempt to improve the thermal management of S/D contacts, an Ohmic contact recess process is proposed to reduce the access resistance and enhance DC/RF performance of AlGaN/GaN HEMTs with a high Al concentration. A contact resistance (RC) of ~0.3 Ω.mm was achieved via optimal recess conditions. Small RC was found to lead to a higher current density at the inner edges of the contact, which resulted in a large increase of channel temperature beneath the S/D contacts. A highly n-doped AlGaN overgrowth layer was proposed to reduce the current density, and thus channel temperature at the Ohmic contacts. Titanium Nitride (TiN) Schottky processing was implemented to minimise the observed strain reduction beneath the gate metal. The optimal Schottky contact is obtained for TiN thicknesses of < 10 nm, which preserves the strain within the AlGaN barrier layer. As a result, Schottky barrier of 1.06 eV, a leakage current of 6 nA and improved linearity of 1.6 was achieved. In addition, C – V and I – V characterisations revealed very low trapping density within the optimised device. Lastly, a new device architecture was proposed to increase the 2-dimentional electron gas (2DEG) density and mobility, without compromising the enhancements of our proposed S/D and gate optimisations. This structure consists of (i) step-graded AlGaN barrier layer to increase strain and (ii) implementing AlN as the interfacial spacer layer