33 research outputs found
Highly Scalable Neuromorphic Hardware with 1-bit Stochastic nano-Synapses
Thermodynamic-driven filament formation in redox-based resistive memory and
the impact of thermal fluctuations on switching probability of emerging
magnetic switches are probabilistic phenomena in nature, and thus, processes of
binary switching in these nonvolatile memories are stochastic and vary from
switching cycle-to-switching cycle, in the same device, and from
device-to-device, hence, they provide a rich in-situ spatiotemporal stochastic
characteristic. This work presents a highly scalable neuromorphic hardware
based on crossbar array of 1-bit resistive crosspoints as distributed
stochastic synapses. The network shows a robust performance in emulating
selectivity of synaptic potentials in neurons of primary visual cortex to the
orientation of a visual image. The proposed model could be configured to accept
a wide range of nanodevices.Comment: 9 pages, 6 figure
Computational Capacity and Energy Consumption of Complex Resistive Switch Networks
Resistive switches are a class of emerging nanoelectronics devices that
exhibit a wide variety of switching characteristics closely resembling
behaviors of biological synapses. Assembled into random networks, such
resistive switches produce emerging behaviors far more complex than that of
individual devices. This was previously demonstrated in simulations that
exploit information processing within these random networks to solve tasks that
require nonlinear computation as well as memory. Physical assemblies of such
networks manifest complex spatial structures and basic processing capabilities
often related to biologically-inspired computing. We model and simulate random
resistive switch networks and analyze their computational capacities. We
provide a detailed discussion of the relevant design parameters and establish
the link to the physical assemblies by relating the modeling parameters to
physical parameters. More globally connected networks and an increased network
switching activity are means to increase the computational capacity linearly at
the expense of exponentially growing energy consumption. We discuss a new
modular approach that exhibits higher computational capacities and energy
consumption growing linearly with the number of networks used. The results show
how to optimize the trade-off between computational capacity and energy
efficiency and are relevant for the design and fabrication of novel computing
architectures that harness random assemblies of emerging nanodevices
Recommended from our members
Versatile stochastic dot product circuits based on nonvolatile memories for high performance neurocomputing and neurooptimization.
The key operation in stochastic neural networks, which have become the state-of-the-art approach for solving problems in machine learning, information theory, and statistics, is a stochastic dot-product. While there have been many demonstrations of dot-product circuits and, separately, of stochastic neurons, the efficient hardware implementation combining both functionalities is still missing. Here we report compact, fast, energy-efficient, and scalable stochastic dot-product circuits based on either passively integrated metal-oxide memristors or embedded floating-gate memories. The circuit's high performance is due to mixed-signal implementation, while the efficient stochastic operation is achieved by utilizing circuit's noise, intrinsic and/or extrinsic to the memory cell array. The dynamic scaling of weights, enabled by analog memory devices, allows for efficient realization of different annealing approaches to improve functionality. The proposed approach is experimentally verified for two representative applications, namely by implementing neural network for solving a four-node graph-partitioning problem, and a Boltzmann machine with 10-input and 8-hidden neurons
Toward large-scale access-transistor-free memristive crossbars
Abstract — Memristive crossbars have been shown to be excel-lent candidates for building an ultra-dense memory system be-cause a per-cell access-transistor may no longer be necessary. However, the elimination of the access-transistor introduces sev-eral parasitic effects due to the existence of partially-selected de-vices during memory accesses, which could limit the scalability of access-transistor-free (ATF) memristive crossbars. In this paper we discuss these challenges in detail and describe some solutions addressing these challenges at multiple levels of design abstrac-tion. I
A data-driven Verilog-A ReRam model
The translation of emerging application concepts that exploit Resistive Random Access Memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model where device current-voltage characteristics and resistive switching rate are expressed as a function of a) bias voltage and b) initial resistive state. The model’s versatility is validated on detailed characterization data, for both filamentary valence change memory and non-filamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing resistive state response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall interoperable with current design tools