Cryptographic application of physical unclonable functions (PUFs)

Physical Unclonable Functions (PUFs) are circuits designed to extract physical randomness from the underlying circuit. This randomness depends on the manufacturing process. It differs for each device enabling chip-level authentication and key generation applications. This thesis has performed research work about PUF based encryption and low power PUFs. First, we present a protocol utilizing a PUF for secure data transmission. Each party has a PUFused for encryption and decryption; this is facilitated by constraining the PUF to be commutative. This framework is evaluated with a primitive permutation network - a barrel shifter. Physical randomness is derived from the delay of different shift paths. Barrel shifter (BS) PUF captures the delay of different shift paths. This delay is entangled with message bits before they are sent across an insecure channel. BS-PUF is implemented using transmission gates; their characteristics ensure same-chip physical commutativity, a necessary property of PUFs designed for encryption. Post-layout simulations of a common centroid layout 8-level barrel shifter in 0.13μm technology assess uniqueness, stability and randomness properties. BS-PUFs pass all selected NIST statistical randomness tests. Stability similar to Ring Oscillator (RO) PUFs under environment variation is shown. Logistic regression of 100,000 plaintext-ciphertext pairs (PCPs) failed to successfully modelBS-PUF behavior. Then we generalize this encryption protocol to work with PUFs other than theBSPUFs. On the other hand, we further explore some low power techniques for building PUFs. Asymmetric layout improved unit path delay variation by as much as 73.2% and uniqueness problem introduced by asymmetric layout is proved to be solvable through Multi-Block entanglement pat-tern. By adopting these 2 techniques, power and area consumption of PUF can be reduced by as much as 44.29% and 39.7%

Statistical modeling of MOS transistor mismatch based on the parameters' autocorrelation function

In this paper a model of MOS transistor mismatch based on autocorrelation function of the statistical parameters is proposed. Firstly a statistical model which maps the statistical behavior of technological parameters considered as a source of errors, into the behavior of device parameters, which depends on device geometry (area and layout) and mutual distances between devices, is derived. Then particular forms for the autocorrelation function are proposed so that expressions for the parameter mismatch variance can be obtained. The model has also been used to analyze mismatch effect on interdigitated and cross-coupled structures