Static Compaction of Test Sequences for Synchronous Sequential Circuits

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit. Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length. compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length. the memory requirements during the test application and the test application time are reduced. Secondly, the extent of test compaction possible for deterministic test sequences indicates that test pattern generators spend a significant amount of time generating test vectors that are not necessary. The compacted test sequences provide a target for more efficient deterministic test generators. Two types of compaction techniques exist: dynamic and static. The dynamic test sequence compaction performs compaction concurrently with the test generation process and often requires modification of the test generator. The static test sequence compaction is done in a post-processing step to the test generation and is independent of the test generation algorithm and process. In the thesis, a new idea for static compaction of test sequences for synchronous sequential circuits has been proposed. Our new method - SUSEM (Set Up Sequence Elimination Method) uses the circuit state information to eliminate some setup sequences for the target faults and consequently reduce the test sequence length. The technique has been used for the test sequences generated by HITEC test generator. ISCAS89 benchmark circuits were used in our experiments, for some circuits which have a large number of target faults and relatively small number of flip-flops, the very significant compactions have been obtained. The more important is that this method can be used to improve the test generation procedure unlike most static compaction methods which blindly or randomly remove parts of test vectors and cannot be used to improve the test generators

Verifying and Monitoring IoTs Network Behavior using MUD Profiles

IoT devices are increasingly being implicated in cyber-attacks, raising community concern about the risks they pose to critical infrastructure, corporations, and citizens. In order to reduce this risk, the IETF is pushing IoT vendors to develop formal specifications of the intended purpose of their IoT devices, in the form of a Manufacturer Usage Description (MUD), so that their network behavior in any operating environment can be locked down and verified rigorously. This paper aims to assist IoT manufacturers in developing and verifying MUD profiles, while also helping adopters of these devices to ensure they are compatible with their organizational policies and track devices network behavior based on their MUD profile. Our first contribution is to develop a tool that takes the traffic trace of an arbitrary IoT device as input and automatically generates the MUD profile for it. We contribute our tool as open source, apply it to 28 consumer IoT devices, and highlight insights and challenges encountered in the process. Our second contribution is to apply a formal semantic framework that not only validates a given MUD profile for consistency, but also checks its compatibility with a given organizational policy. We apply our framework to representative organizations and selected devices, to demonstrate how MUD can reduce the effort needed for IoT acceptance testing. Finally, we show how operators can dynamically identify IoT devices using known MUD profiles and monitor their behavioral changes on their network.Comment: 17 pages, 17 figures. arXiv admin note: text overlap with arXiv:1804.0435

Stuck-at-fault test set compaction

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.Includes bibliographical references (leaf 21).Proper testing of manufactured digital circuits is critical to ensuring the number of defective parts is minimized. Automated test pattern generation tools are created in order to produce test patterns that can be applied with the intention of identifying as many defective parts as possible. The increasing complexity of digital circuit designs causes this task to continue to increase in difficulty. At the same time, the amount of time dedicated to testing should be kept constant. Therefore, it is crucial to limit the number of test patterns that are applied to any given circuit. Additionally, tester memories may limit the number of test patterns that may be applied at one time. This research demonstrates several existing methods of compaction and introduces a new method for measuring the contribution of each test pattern. Both static and dynamic compaction methods were implemented and evaluated in terms of final test pattern set size and diversity of excitation. The program resulting from this research has been shown to equal or surpass an existing automated test pattern generation tool

Transition-fault test generation

Due to the character of the original source materials and the nature of batch digitization, quality control issues may be present in this document. Please report any quality issues you encounter to [email protected], referencing the URI of the item.Includes bibliographical references (leaf 18).After an integrated circuit is manufactured, it must be tested to insure that it is not defective. Specifically, timing defects are becoming increasingly important to detect because of the decreasing process geometries and increasing clock rates. One way to detect these timing defects is to apply test patterns to the integrated circuit that are generated using the transition-fault model. Unfortunately, industry's current transition-fault test generation schemes produce test sets that are too large to store in the memory of the tester. The proposed methods of test generation utilize stuck-at-fault tests to create transition-fault test sets of a smaller size. Greedy algorithms are used in the generation of both the stuck-at-fault and transition-fault tests. In addition, various methods of test set compaction are explored to further reduce the size of the test sets. This research demonstrates an effective way to generate compact transition-fault test sets for a benchmark circuit and holds great promise for application to large commercial circuits

Radiative Falloff in Neutron Star Spacetimes

We systematically study late-time tails of scalar waves propagating in neutron star spacetimes. We consider uniform density neutron stars, for which the background spacetime is analytic and the compaction of the star can be varied continously between the Newtonian limit 2M/R << 1 and the relativistic Buchdahl limit 2M/R = 8/9. We study the reflection of a finite wave packet off neutron stars of different compactions 2M/R and find that a Newtonian, an intermediate, and a highly relativistic regime can be clearly distinguished. In the highly relativistic regime, the reflected signal is dominated by quasi-periodic peaks, which originate from the wave packet bouncing back and forth between the center of the star and the maximum of the background curvature potential at R ~ 3 M. Between these peaks, the field decays according to a power-law. In the Buchdahl limit 2M/R -> 8/9 the light travel time between the center and the maximum or the curvature potential grows without bound, so that the first peak arrives only at infinitely late time. The modes of neutron stars can therefore no longer be excited in the ultra-relativistic limit, and it is in this sense that the late-time radiative decay from neutron stars looses all its features and gives rise to power-law tails reminiscent of Schwarzschild black holes.Comment: 10 pages, 7 figures, to appear in PR

Simple, compact and robust approximate string dictionary

This paper is concerned with practical implementations of approximate string dictionaries that allow edit errors. In this problem, we have as input a dictionary $D$ of $d$ strings of total length $n$ over an alphabet of size $\sigma$. Given a bound $k$ and a pattern $x$ of length $m$, a query has to return all the strings of the dictionary which are at edit distance at most $k$ from $x$, where the edit distance between two strings $x$ and $y$ is defined as the minimum-cost sequence of edit operations that transform $x$ into $y$. The cost of a sequence of operations is defined as the sum of the costs of the operations involved in the sequence. In this paper, we assume that each of these operations has unit cost and consider only three operations: deletion of one character, insertion of one character and substitution of a character by another. We present a practical implementation of the data structure we recently proposed and which works only for one error. We extend the scheme to $2\leq k<m$. Our implementation has many desirable properties: it has a very fast and space-efficient building algorithm. The dictionary data structure is compact and has fast and robust query time. Finally our data structure is simple to implement as it only uses basic techniques from the literature, mainly hashing (linear probing and hash signatures) and succinct data structures (bitvectors supporting rank queries).Comment: Accepted to a journal (19 pages, 2 figures

Deep tillage tool optimization by means of finite element method: Case study for a subsoiler tine

Technologies and computer capacity currently available allow us to employ design software and numerical methods to solve complicated problems in very wide disciplines of engineering. It is also important for researches in agriculture. This study focused on obtaining optimum geometry parameters of a subsoiler tine by using computer aided engineering (CAE) applications. A field experiment was conducted to determine draft force of the subsoiler. The results from the experimental study were used in the finite element analysis (FEA) to simulate stress distributions on the subsoiler tine. The maximum equivalent stress of 432.49 MPa was obtained in the FEA. Visual investigations and FEA results showed that according to the tine’s material yield stress point of 355 MPa, plastic deformation was evident. Based on the FEA results, an optimization study was undertaken to obtain optimum geometry parameters without the occurrence of plastic deformation. According to the optimization study results, the optimum parameters of the tine geometry and maximum equivalent stress of 346.61 MPa were obtained. In addition to this, the total mass of the tine was reduced by about 0.367 kg