85 research outputs found
RowHammer: Reliability Analysis and Security Implications
As process technology scales down to smaller dimensions, DRAM chips become
more vulnerable to disturbance, a phenomenon in which different DRAM cells
interfere with each other's operation. For the first time in academic
literature, our ISCA paper exposes the existence of disturbance errors in
commodity DRAM chips that are sold and used today. We show that repeatedly
reading from the same address could corrupt data in nearby addresses. More
specifically: When a DRAM row is opened (i.e., activated) and closed (i.e.,
precharged) repeatedly (i.e., hammered), it can induce disturbance errors in
adjacent DRAM rows. This failure mode is popularly called RowHammer. We tested
129 DRAM modules manufactured within the past six years (2008-2014) and found
110 of them to exhibit RowHammer disturbance errors, the earliest of which
dates back to 2010. In particular, all modules from the past two years
(2012-2013) were vulnerable, which implies that the errors are a recent
phenomenon affecting more advanced generations of process technology.
Importantly, disturbance errors pose an easily-exploitable security threat
since they are a breach of memory protection, wherein accesses to one page
(mapped to one row) modifies the data stored in another page (mapped to an
adjacent row).Comment: This is the summary of the paper titled "Flipping Bits in Memory
Without Accessing Them: An Experimental Study of DRAM Disturbance Errors"
which appeared in ISCA in June 201
Coordinate Channel-Aware Page Mapping Policy and Memory Scheduling for Reducing Memory Interference Among Multimedia Applications
"© 2017 IEEE. Personal use of this material is permitted. Permissíon from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertisíng or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works."[EN] In a modern multicore system, memory is shared among more and more concurrently running multimedia applications. Therefore, memory contention and interference are more andmore serious, inducing system performance degradation significantly, the performance degradation of each thread differently, unfairness in resource sharing, and priority inversion, even starvation. In this paper, we propose an approach of coordinating channel-aware page mapping policy and memory scheduling (CCPS) to reduce intermultimedia application interference in a memory system. The idea is to map the data of different threads to different channels, together with memory scheduling. The key principles of the policies of page mapping and memory scheduling are: 1) the memory address space, the thread priority, and the load balance; and 2) prioritizing a low-memory request thread, a row-buffer hit access, and an older request. We evaluate the CCPS on a variety of mixed single-thread and multithread benchmarks and system configurations, and we compare them with four previously proposed state-of-the-art interference-reducing policies. Experimental results demonstrate that the CCPS improves the performance while reducing the energy consumption significantly; moreover, the CCPS incurs a much lower hardware overhead than the current existing policies.This work was supported in part by the Qing Lan Project; by the National Science Foundation of China under Grant 61003077, Grant 61100193, and Grant 61401147; and by the Zhejiang Provincial Natural Science Foundation under Grant LQ14F020011.Jia, G.; Han, G.; Li, A.; Lloret, J. (2017). Coordinate Channel-Aware Page Mapping Policy and Memory Scheduling for Reducing Memory Interference Among Multimedia Applications. IEEE Systems Journal. 11(4):2839-2851. https://doi.org/10.1109/JSYST.2015.2430522S2839285111
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs
The initial location of data in DRAMs is determined and controlled by the
'address-mapping' and even modern memory controllers use a fixed and
run-time-agnostic address mapping. On the other hand, the memory access pattern
seen at the memory interface level will dynamically change at run-time. This
dynamic nature of memory access pattern and the fixed behavior of address
mapping process in DRAM controllers, implied by using a fixed address mapping
scheme, means that DRAM performance cannot be exploited efficiently. DReAM is a
novel hardware technique that can detect a workload-specific address mapping at
run-time based on the application access pattern which improves the performance
of DRAMs. The experimental results show that DReAM outperforms the best
evaluated address mapping on average by 9%, for mapping-sensitive workloads, by
2% for mapping-insensitive workloads, and up to 28% across all the workloads.
DReAM can be seen as an insurance policy capable of detecting which scenarios
are not well served by the predefined address mapping
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