49,662 research outputs found
A design tool for high-resolution high-frequency cascade continuous- time ÎŁâ modulators
Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran
Canaria, SpainThis paper introduces a CAD methodology to assist the de
signer in the implementation of continuous-time (CT) cas-
cade
ÎŁâ
modulators. The salient features of this methodology ar
e: (a) flexible behavioral modeling for optimum accuracy-
efficiency trade-offs at different stages of the top-down
synthesis process; (b) direct synthesis in the continuous-time
domain for minimum circuit complexity and sensitivity; a
nd (c) mixed knowledge-based and optimization-based architec-
tural exploration and specification transmission for enhanced
circuit performance. The applicability of this methodology
will be illustrated via the design of a 12 bit 20 MHz CT
ÎŁâ
modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y EducaciĂłn TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec
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Automatic synthesis of analog layout : a survey
A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon
The future of computing beyond Moore's Law.
Moore's Law is a techno-economic model that has enabled the information technology industry to double the performance and functionality of digital electronics roughly every 2 years within a fixed cost, power and area. Advances in silicon lithography have enabled this exponential miniaturization of electronics, but, as transistors reach atomic scale and fabrication costs continue to rise, the classical technological driver that has underpinned Moore's Law for 50 years is failing and is anticipated to flatten by 2025. This article provides an updated view of what a post-exascale system will look like and the challenges ahead, based on our most recent understanding of technology roadmaps. It also discusses the tapering of historical improvements, and how it affects options available to continue scaling of successors to the first exascale machine. Lastly, this article covers the many different opportunities and strategies available to continue computing performance improvements in the absence of historical technology drivers. This article is part of a discussion meeting issue 'Numerical algorithms for high-performance computational science'
Requirements for a Research-oriented IC Design System
Computer-aided design techniques for integrated circuits grown in an incremental way, responding to various perceived needs, so that today there are a number of useful programs for logic generation, simulation at various levels, test preparation, artwork generation and
analysis (including design rule checking), and interactive graphical editing. While the design of many circuits has benefitted from these programs, when industry wants to produce a high-volume part, the design and layout are done manually, followed by digitizing and
perhaps some graphic editing before it is converted to pattern generation format, leading to the often heard statement that computer-aided design of integrated circuits doesn't work. If progress is to be made, it seems clear that the entire design process has to be thought through in basic terms, and much more attention must
be paid to the way in which computational techniques can complement the designer's abilities. Currently, it is appropriate to try to characterize the design process in abstract terms, so that implementation and technological biases don't cloud the view of a desired system. In this paper, we briefly describe the conversion of
algorithms to masks at a very general level, and then describe several projects at MIT which aim to provide contributions to an integrated design system. It is emphasized that no complete system design exists
now at MIT, and that we believe that general design considerations must constantly be tested by building (and rebuilding) the various subcomponents, the structure of which is guided by our view of the overall design process
VLSI Architecture and Design
Integrated circuit technology is rapidly approaching a state where feature sizes of one micron or less are tractable. Chip sizes are increasing slowly. These two developments result in considerably increased complexity in chip design. The physical characteristics of integrated circuit technology are also changing. The cost of communication will be dominating making new architectures and algorithms both feasible and desirable. A large
number of processors on a single chip will be possible. The cost of communication will make
designs enforcing locality superior to other types of designs.
Scaling down feature sizes results in increase of the delay that wires introduce. The delay even of metal wires will become significant. Time tends to be a local property which will make the design of globally synchronous systems more difficult. Self-timed systems will eventually become a necessity.
With the chip complexity measured in terms of logic devices increasing by more than an order of magnitude over the next few years the importance of efficient design methodologies and tools become crucial. Hierarchical and structured design are ways of dealing with the complexity of chip design. Structered design focuses on the information
flow and enforces a high degree of regularity. Both hierarchical and structured design encourage the use of cell libraries. The geometry of the cells in such libraries should be parameterized so that for instance cells can adjust there size to neighboring cells and make the proper interconnection. Cells with this quality can be used as a basis for "Silicon Compilers"
Programming Quantum Computers Using Design Automation
Recent developments in quantum hardware indicate that systems featuring more
than 50 physical qubits are within reach. At this scale, classical simulation
will no longer be feasible and there is a possibility that such quantum devices
may outperform even classical supercomputers at certain tasks. With the rapid
growth of qubit numbers and coherence times comes the increasingly difficult
challenge of quantum program compilation. This entails the translation of a
high-level description of a quantum algorithm to hardware-specific low-level
operations which can be carried out by the quantum device. Some parts of the
calculation may still be performed manually due to the lack of efficient
methods. This, in turn, may lead to a design gap, which will prevent the
programming of a quantum computer. In this paper, we discuss the challenges in
fully-automatic quantum compilation. We motivate directions for future research
to tackle these challenges. Yet, with the algorithms and approaches that exist
today, we demonstrate how to automatically perform the quantum programming flow
from algorithm to a physical quantum computer for a simple algorithmic
benchmark, namely the hidden shift problem. We present and use two tool flows
which invoke RevKit. One which is based on ProjectQ and which targets the IBM
Quantum Experience or a local simulator, and one which is based on Microsoft's
quantum programming language Q.Comment: 10 pages, 10 figures. To appear in: Proceedings of Design, Automation
and Test in Europe (DATE 2018
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
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