32 research outputs found
Online Scheduled Execution of Quantum Circuits Protected by Surface Codes
Quantum circuits are the preferred formalism for expressing quantum
information processing tasks. Quantum circuit design automation methods mostly
use a waterfall approach and consider that high level circuit descriptions are
hardware agnostic. This assumption has lead to a static circuit perspective:
the number of quantum bits and quantum gates is determined before circuit
execution and everything is considered reliable with zero probability of
failure. Many different schemes for achieving reliable fault-tolerant quantum
computation exist, with different schemes suitable for different architectures.
A number of large experimental groups are developing architectures well suited
to being protected by surface quantum error correcting codes. Such circuits
could include unreliable logical elements, such as state distillation, whose
failure can be determined only after their actual execution. Therefore,
practical logical circuits, as envisaged by many groups, are likely to have a
dynamic structure. This requires an online scheduling of their execution: one
knows for sure what needs to be executed only after previous elements have
finished executing. This work shows that scheduling shares similarities with
place and route methods. The work also introduces the first online schedulers
of quantum circuits protected by surface codes. The work also highlights
scheduling efficiency by comparing the new methods with state of the art static
scheduling of surface code protected fault-tolerant circuits.Comment: accepted in QI
Energy Scalability of On-Chip Interconnection Networks in Multicore Architectures
On-chip interconnection networks (OCNs) such as point-to-point networks and buses form the communication backbone in systems-on-a-chip, multicore processors, and tiled processors. OCNs can consume significant portions of a chip's energy budget, so analyzing their energy consumption early in the design cycle becomes important for architectural design decisions. Although numerous studies have examined OCN implementation and performance, few have examined energy. This paper develops an analytical framework for energy estimation in OCNs and presents results based on both analytical models of communication patterns and real network traces from applications running on a tiled multicore processor. Our analytical framework supports arbitrary OCN topologies under arbitrary communication patterns while accounting for wire length, switch energy, and network contention. It is the first to incorporate the effects of communication locality and network contention, and use real traces extensively. This paper compares the energy of point-to-point networks against buses under varying degrees of communication locality. The results indicate that, for 16 or more processors, a one-dimensional and a two-dimensional point-to-point network provide 66% and 82% energy savings, respectively, over a bus assuming that processors communicate with equal likelihood. The energy savings increase for patterns which exhibit locality. For the two-dimensional point-to-point OCN of the Raw tiled microprocessor, contention contributes a maximum of just 23% of the OCN energy, using estimated values for channel, switch control logic, and switch queue buffer energy of 34.5pJ, 17pJ, and 12pJ, respectively. Our results show that the energy-delay product per message decreases with increasing processor message injection rate
Software based instruction caching for the RAW architecture
Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.Includes bibliographical references (p. 39).by Jason Eric Miller.S.B.and M.Eng