An efficient analytical placement algorithm using cell shifting, iterative local refinement and a hybrid net model

In this thesis, we present FastPlace-a fast, iterative, flat placement algorithm for large scale standard cell designs in the fixed-die context. FastPlace is based on the quadratic placement approach. The quadratic approach formulates the wirelength minimization problem as a convex quadratic program, which can be solved analytically by some efficient techniques. However, the quadratic approach in general suffers from some drawbacks. First, the resulting placement has a lot of overlap among cells. Second, the resulting total wirelength may be long as the quadratic wirelength objective is only an indirect measure of the total linear wirelength. Third, existing net models tend to create a lot of non-zero entries in the connectivity matrix while modeling the netlist and this slows down the quadratic program solver. These problems are handled as follows: (1) A Cell Shifting technique is proposed to generate an evenly distribute global placement from the quadratic program solution. This technique is very efficient and produces a high-quality global placement with even cell distribution. (2) An Iterative Local Refinement technique is proposed to reduce the wirelength according to the half-perimeter bounding rectangle measure. This technique is very effective as it makes use of the wirelength and cell distribution information provided by a coarse global placement. (3) A Hybrid Net Model is proposed which is a combination of the traditional clique and star models. This net model significantly reduces the number of non-zero entries in the connectivity matrix. It results in a significant speed-up of the solver as compared to using it with the traditional clique model. Experimental results show that the run-time of FastPlace is of the order O(n1·412), where n is the circuit size given by the number of pins. Also, the current implementation when tested on 18 Standard Cell benchmark circuits is on average 11.0 and 82.7 times faster than existing academic placers Capo and Dragon respectively

The Effect of Storytelling on Iranian EFL Learners’ Vocabulary Retention

This paper presents the results of a study on utilizing two storytelling techniques, summarizing and strip story arrangement, in an EFL context. It focused on exploring which type of storytelling technique was more effective and thus could help EFL learners master the new words better. In was carried out in a private language school in Tehran, Iran. The participants were 105 learners who were selected from 160 elementary learners based on their performance on Oxford Placement Test as the test of homogenization. Three groups were formed, two experimental and one control group with 35 subjects in each. The learners in the summarizing group used the new words to summarize the stories in their written and spoken tasks and the learners in the other experimental group, strip story arrangement group, were asked to arrange some split sentences in their personal drafts. After thirty treatment sessions, the learners were given the posttest. The three groups’ performances on the posttest were compared by one way ANOVA. The results showed that the learners in summarizing group performed better than strip story arrangement group and both groups outperformed the control group

Experimental Study of Various Techniques to Protect Ice-Rich Cut Slopes

INE/AUTC 15.08 and INE/AUTC 13.07 (2013) Construction Repor

Methodology for standard cell compliance and detailed placement for triple patterning lithography

As the feature size of semiconductor process further scales to sub-16nm technology node, triple patterning lithography (TPL) has been regarded one of the most promising lithography candidates. M1 and contact layers, which are usually deployed within standard cells, are most critical and complex parts for modern digital designs. Traditional design flow that ignores TPL in early stages may limit the potential to resolve all the TPL conflicts. In this paper, we propose a coherent framework, including standard cell compliance and detailed placement to enable TPL friendly design. Considering TPL constraints during early design stages, such as standard cell compliance, improves the layout decomposability. With the pre-coloring solutions of standard cells, we present a TPL aware detailed placement, where the layout decomposition and placement can be resolved simultaneously. Our experimental results show that, with negligible impact on critical path delay, our framework can resolve the conflicts much more easily, compared with the traditional physical design flow and followed layout decomposition

BriskStream: Scaling Data Stream Processing on Shared-Memory Multicore Architectures

We introduce BriskStream, an in-memory data stream processing system (DSPSs) specifically designed for modern shared-memory multicore architectures. BriskStream's key contribution is an execution plan optimization paradigm, namely RLAS, which takes relative-location (i.e., NUMA distance) of each pair of producer-consumer operators into consideration. We propose a branch and bound based approach with three heuristics to resolve the resulting nontrivial optimization problem. The experimental evaluations demonstrate that BriskStream yields much higher throughput and better scalability than existing DSPSs on multi-core architectures when processing different types of workloads.Comment: To appear in SIGMOD'1